# US 10,374,605 B2 · Logical elements with switchable connections in a reconfigurable fabric > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,374,605 B2 - Document ID: US10374605B2 - Status: Granted - Kind: B2 - Application number: 16/176,922 - Filed: 2018-10-31 - Published: 2019-03-07 - Granted: 2019-08-06 - Earliest claimed: 2013-11-02 - Assignees: Wave Computing, Inc. - Applicants: Wave Computing, Inc. - Inventors: Christopher John Nicol - Web page: https://patentgrep.com/patent/US10374605B2 ## CPC - H03K 19/017581: {programmable} - H03K 19/1776: for memories - H03K 19/17764: for reliability - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract Techniques are disclosed for designing a reconfigurable fabric. The reconfigurable fabric is designed using logical elements, configurable connections between and among the logical elements, and rotating circular buffers. The circular buffers contain configuration instructions. The configuration instructions control connections between and among logical elements. The logical elements change operation based on the instructions that rotate through the circular buffers. Clusters of logical elements are interconnected by a switching fabric. Each cluster contains processing elements, storage elements, and switching elements. A circular buffer within a cluster contains multiple switching instructions to control the flow of data throughout the switching fabric. The circular buffer provides a pipelined execution of switching instructions for the implementation of multiple functions. Each cluster contains multiple processing elements, and each cluster further comprises an additional circular buffer for each processing element. Logical operations are controlled by the circular buffers. ## Claims ### Claim 1 A computer-implemented method of designing a reconfigurable fabric comprising: implementing a plurality of logical elements; connecting configurable connections between and among the plurality of logical elements; and implementing a plurality of rotating circular buffers residing on a semiconductor chip where the plurality of rotating circular buffers contain configuration instructions which control different configurable connections between and among the plurality of logical elements and dynamically change operation of the logical elements based on the rotating of a circular buffer within the plurality of rotating circular buffers, wherein the plurality of rotating circular buffers have differing lengths and resynchronize with a zeroth pipeline stage for each of the plurality of rotating circular buffers. ### Claim 2 (depends on 1) The method of claim 1 wherein the rotating of the circular buffer within the plurality of rotating circular buffers enables two or more logic functions to be implemented in run time. ### Claim 3 (depends on 1) The method of claim 1 wherein the configuration instructions are preprocessed by a compiler and statically scheduled to avoid collisions among the plurality of logical elements. ### Claim 4 (depends on 3) The method of claim 3 wherein the preprocessing inserts further instructions to prevent the collisions. ### Claim 5 (depends on 4) The method of claim 4 wherein the further instructions include one or more of storage instructions, sleep instructions, or no-op instructions. ### Claim 6 (depends on 3) The method of claim 3 further comprising replacing multiple instructions with a single fan-in instruction in preprocessing. ### Claim 7 (depends on 1) The method of claim 1 wherein the configurable connections are time multiplexed. ### Claim 8 (depends on 1) The method of claim 1 wherein the circular buffer within the plurality of rotating circular buffers is programmed and instructions are preprocessed to generate input to the circular buffer within the plurality of rotating circular buffers for dynamic programming. ### Claim 9 (depends on 1) The method of claim 1 wherein the circular buffer within the plurality of rotating circular buffers controls passing data to a quad of processing elements through switching elements, where each of the quad of processing elements is controlled by four other circular buffers, where data is passed back through the switching elements from the quad of processing elements where the switching elements are again controlled by the circular buffer within the plurality of rotating circular buffers. ### Claim 10 (depends on 1) The method of claim 1 wherein a column within the circular buffer within the plurality of rotating circular buffers can be skipped in a cycle. ### Claim 11 (depends on 10) The method of claim 10 wherein not skipping indicates a valid instruction. ### Claim 12 (depends on 1) The method of claim 1 wherein the plurality of logical elements includes a processing element that can be placed in a sleep state where the sleep state is exited based on data being valid. ### Claim 13 (depends on 12) The method of claim 12 wherein the sleep state can be entered by an instruction within the processing element. ### Claim 14 (depends on 12) The method of claim 12 wherein the processing element wakes up from the sleep state when valid data is applied to inputs of the processing element. ### Claim 15 (depends on 14) The method of claim 14 wherein the sleep state can only be exited by stimulus external to the processing element and not based on programming of the processing element. ### Claim 16 (depends on 15) The method of claim 15 wherein the sleep state is exited based on an instruction applied to a switching fabric. ### Claim 17 (depends on 1) The method of claim 1 wherein the configurable connections provide three-dimensional routing. ### Claim 18 (depends on 1) The method of claim 1 further comprising storage elements coupled to the configurable connections wherein the storage elements include one or more of registers, caches, or on-chip memories. ### Claim 19 (depends on 18) The method of claim 18 wherein the storage elements store data while the configurable connections are busy with other data. ### Claim 20 (depends on 1) The method of claim 1 wherein the configurable connections enable bypassing of neighboring logical elements. ### Claim 21 (depends on 1) The method of claim 1 wherein communication through the configurable connections is based on data being valid. ### Claim 22 (depends on 1) The method of claim 1 where collisions are avoided by intermediate data being stored in registers for pipeline cycles before being sent to an output port for a cluster. ### Claim 23 A computer program embodied in a non-transitory computer readable medium for implementation of a reconfigurable fabric, the computer program comprising code which configures one or more processors to perform operations of: designing a reconfigurable fabric by: implementing a plurality of logical elements; connecting configurable connections between and among the plurality of logical elements; and implementing a plurality of rotating circular buffers residing on a semiconductor chip where the plurality of rotating circular buffers contain configuration instructions which control different configurable connections between and among the plurality of logical elements and dynamically change operation of the logical elements based on the rotating of a circular buffer within the plurality of rotating circular buffers, wherein the plurality of rotating circular buffers have differing lengths and resynchronize with a zeroth pipeline stage for each of the plurality of rotating circular buffers. ### Claim 24 A computer system for implementation of a reconfigurable fabric comprising: a memory which stores instructions; and one or more processors coupled to the memory, wherein the one or more processors are configured to: design a reconfigurable fabric by: implementing a plurality of logical elements; connecting configurable connections between the plurality of logical elements; and implementing a plurality of rotating circular buffers residing on a semiconductor chip where the plurality of rotating circular buffers contain configuration instructions which control different configurable connections between the plurality of logical elements and dynamically change operation of the logical elements based on the rotating of a circular buffer within the plurality of rotating circular buffers, wherein the plurality of rotating circular buffers have differing lengths and resynchronize with a zeroth pipeline stage for each of the plurality of rotating circular buffers.