# US 10,374,587 B2 · Phase shift clock for digital LLC converter > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,374,587 B2 - Document ID: US10374587B2 - Status: Granted - Kind: B2 - Application number: 15/695,863 - Filed: 2017-09-05 - Published: 2017-12-21 - Granted: 2019-08-06 - Earliest claimed: 2016-05-12 - Assignees: Infineon Technologies Austria AG - Applicants: Infineon Technologies Austria AG - Inventors: Martin Feldtkeller - Web page: https://patentgrep.com/patent/US10374587B2 ## CPC - H03K 5/135: by the use of time reference signals, e.g. clock signals - H03K 17/687: the devices being field-effect transistors - H03K 19/017509: {Interface arrangements} - H03K 2005/00286: {Phase shifter, i.e. the delay between the output and input pulse is dependent on the frequency, and such that a phase difference is obtained independent of the frequency} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract The techniques of this disclosure may digitally generate a driver signal with a period (or frequency) at a finer resolution than can be achieved by simply counting clock cycles of a system clock. The driver signal may be configured to trigger based on single output clock signal that may be phase-shifted relative to the master system clock. A clock phase shift circuit may increment the phase shift of the output clock signal to any fraction relative to the master system clock. A driver signal generated based on the phase-shifted output clock may achieve the high resolution in frequency desirable when controlling some pulse-width modulated circuits, such as an LLC converter. ## Claims ### Claim 1 A system comprising: a single, input clock, wherein the single, input clock defines a master input clock frequency; a clock phase shift circuit, configured to: output a second clock signal wherein a second clock signal frequency is approximately the same frequency as the master input clock frequency, and increment a phase shift of the second clock signal relative to the single, input clock, wherein the clock phase shift circuit increments the phase shift in response to a capacitor charge current amperage level; and a control unit configured to: receive the second clock signal, generate a driver signal at a predetermined frequency, wherein the phase shift of the second clock signal relative to the master input clock sets a fractional part of a frequency ratio between the master input clock frequency and the predetermined frequency, and wherein the predetermined frequency of the driver signal comprises an integer part generated by counting clock cycles and the fractional part generated by shifting the phase of the second clock signal. ### Claim 2 (depends on 1) The system of claim 1, wherein the integer part comprises a multiple of the single, input clock generated by counting clock cycles of the second clock signal. ### Claim 3 (depends on 1) The system of claim 1, wherein the second clock signal contains no discontinuities or short pulses when the phase shift exceeds multiples of 360 degrees. ### Claim 4 (depends on 1) The system of claim 1, wherein the clock phase shift circuit increments the phase shift based on a phase control word. ### Claim 5 (depends on 1) The system of claim 1, wherein the clock phase shift circuit is further configured to increment the phase during times when there is no time event and stop incrementing the phase during times where there is a time event. ### Claim 6 (depends on 1) The system of claim 1, wherein the increment of the phase shift of the second clock signal increases relative to the single, input clock. ### Claim 7 (depends on 1) The system of claim 1, wherein the driver signal is an LLC half-bridge driver signal. ### Claim 8 (depends on 7) The system of claim 7, wherein the control unit is further configured to generate a driver signal comprising a high-side gate driver signal and a low-side gate driver signal. ### Claim 9 (depends on 8) The system of claim 8, wherein the high-side gate driver signal is an ultra-high voltage (UHV) signal. ### Claim 10 (depends on 8) The system of claim 8, wherein the driver signal is compatible to drive the LLC half-bridge, wherein the LLC half-bridge includes gallium nitride (GaN) components. ### Claim 11 (depends on 1) The system of claim 1, wherein the driver signal further comprises a dead time signal, wherein the dead time signal is substantially synchronized to the second clock signal. ### Claim 12 (depends on 1) The system of claim 1, wherein the control unit is further configured to generate a level shifter signal, wherein the level shifter signal is substantially synchronized to the second clock signal. ### Claim 13 (depends on 1) The system of claim 1, further comprising an LLC converter, wherein the LLC converter is configured to receive the driver signal. ### Claim 14 (depends on 13) The system of claim 13, wherein the LLC converter comprises a piezo transformer. ### Claim 15 (depends on 13) The system of claim 13, wherein the LLC converter comprises a high-side switch and a low-side switch. ### Claim 16 (depends on 15) The system of claim 15, wherein the high-side switch is an ultra-high voltage (UHV) switch. ### Claim 17 (depends on 15) The system of claim 15, wherein the high-side switch and the low-side switch comprise gallium nitride (GaN). ### Claim 18 (depends on 13) The system of claim 13, wherein the LLC converter is configured to operate at frequency of at least one MHz. ### Claim 19 (depends on 13) The system of claim 13, wherein the LLC converter is configured for high voltage direct current (DC) to alternating current (AC) conversion.