# US 10,374,584 B1 · Low power retention flip-flop with level-sensitive scan circuitry > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,374,584 B1 - Document ID: US10374584B1 - Status: Granted - Kind: B1 - Application number: 15/916,130 - Filed: 2018-03-08 - Granted: 2019-08-06 - Earliest claimed: 2018-03-08 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Charles Augustine; Muhammad Khellah; Arvind Raman; Feroze Merchant; Ashish Choubal - Web page: https://patentgrep.com/patent/US10374584B1 ## CPC - H03K 3/0372: {of the primary-secondary type} - G01R 31/318541: {Scan latches or cell details} - H03K 3/0375: {provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails (digital storage cells each combining volatile and non-volatile storage properties G11C14/00)} - H03K 3/35625: {using complementary field-effect transistors} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) ## Abstract An apparatus comprising: a flip-flip comprising a master stage and a slave stage, wherein the slave stage is coupled to the master stage, wherein the master and slave stages are coupled to a first power supply rail; and a scan circuitry coupled to the slave stage of the flip-flip, wherein at least a portion of the scan circuitry is coupled to a second power supply rail. ## Claims ### Claim 1 An apparatus comprising: a flip-flip comprising a master stage and a slave stage, wherein the slave stage is coupled to the master stage, wherein the master and slave stages are coupled to a first power supply rail; and a scan circuitry coupled to the slave stage of the flip-flip, wherein at least a portion of the scan circuitry is coupled to a second power supply rail, wherein the scan circuitry comprises an inverter connected to the slave stage, wherein the inverter is controllable by a scan signal, and wherein the inverter is coupled to the second power supply rail. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the first power supply rail is to provide a first power supply, wherein the second power supply rail is to provide a second power supply, and wherein when the first power supply is turned off, the second power supply is still on. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein the inverter is a first inverter, wherein the scan signal is generated by a second inverter, and wherein the first and second inverters are coupled to the second power supply rail. ### Claim 4 (depends on 3) The apparatus of claim 3, wherein the scan circuitry comprises a memory circuitry coupled to an output of the first inverter. ### Claim 5 (depends on 4) The apparatus of claim 4 comprises a third inverter coupled to an output of the memory circuitry. ### Claim 6 (depends on 5) The apparatus of claim 5 comprises a fourth inverter coupled to an output of the third inverter and an input of the first inverter, wherein the fourth inverter is controllable by a sleep signal. ### Claim 7 (depends on 6) The apparatus of claim 6, wherein the sleep signal is generated by a fifth inverter coupled to the first supply rail. ### Claim 8 An apparatus comprising: a flip-flop; and a scan circuitry coupled to the flip-flip, wherein the scan circuitry is to retain data from the flip-flop when the flip-flop is in low power state, wherein the scan circuitry comprises an inverter connected to a slave stage of the flip-flop, wherein the inverter is controllable by a scan signal, and wherein the inverter is coupled to a power supply rail separate from a power supply coupled to the flip-flop. ### Claim 9 (depends on 8) The apparatus of claim 8, wherein the scan circuitry is to store the retained data back to the flip-flop when the flip-flop transitions from the low power state to a high power state. ### Claim 10 (depends on 8) The apparatus of claim 8, wherein the scan circuitry is to scan data from the flip-flop to a scan output during a scan mode. ### Claim 11 (depends on 8) The apparatus of claim 8, wherein a portion of the scan circuitry is coupled to the power supply rail separate from the power supply rail coupled to the flip-flop. ### Claim 12 (depends on 8) The apparatus of claim 8, wherein an input of the inverter is coupled to an n-type pull-down device, and wherein the n-type pull-down device is controllable by a power mode signal which indicates the low power state. ### Claim 13 A system comprising: a memory; a processor coupled to the memory, wherein the processor includes a sequential circuitry including: a flip-flip comprising a master stage and a slave stage, wherein the slave stage is coupled to the master stage, wherein the master and slave stages are coupled to a first power supply rail; and a scan circuitry coupled to the slave stage of the flip-flip, wherein at least a portion of the scan circuitry is coupled to a second power supply rail, wherein the scan circuitry comprises an inverter connected to the slave stage, wherein the inverter is controllable by a scan signal, and wherein the inverter is coupled to the second power supply rail; and a wireless interface to allow the processor to communicate with another device. ### Claim 14 (depends on 13) The system of claim 13, wherein the first power supply rail is to provide a first power supply, wherein the second power supply rail is to provide a second power supply, and wherein when the first power supply is turned off, the second power supply is still on. ### Claim 15 (depends on 13) The system of claim 13, wherein the inverter is a first inverter, wherein the scan signal is generated by a second inverter, wherein the first and second inverters are coupled to the second power supply rail. ### Claim 16 (depends on 15) The system of claim 15, wherein the scan circuitry comprises a memory circuitry coupled to an output of the first inverter. ### Claim 17 (depends on 16) The system of claim 16 comprises a third inverter coupled to an output of the memory circuitry. ### Claim 18 (depends on 17) The system of claim 17 comprises a fourth inverter coupled to an output of the third inverter and an input of the first inverter, wherein the fourth inverter is controllable by a sleep signal. ### Claim 19 (depends on 18) The system of claim 18, wherein the sleep signal is generated by a fifth inverter coupled to the first supply rail.