# US 10,374,583 B1 · Dynamic hysteresis circuit

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- Number: US 10,374,583 B1
- Document ID: US10374583B1
- Status: Granted
- Kind: B1
- Application number: 15/943,341
- Filed: 2018-04-02
- Granted: 2019-08-06
- Earliest claimed: 2018-04-02
- Assignees: Analog Devices, Inc.
- Applicants: Analog Devices, Inc.
- Inventors: Piotr Olejarz; Daniel Saari; Ara Arakelian
- Web page: https://patentgrep.com/patent/US10374583B1

## CPC

- H03K 3/02337: {Bistables with hysteresis, e.g. Schmitt trigger (non-regenerative amplitude discriminators G01R19/165)}
- G06F 13/24: using interrupt (G06F13/32 takes precedence)
- G06F 13/385: {for adaptation of a particular data processing system to different peripheral devices}
- G06F 13/4072: {Drivers or receivers (G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002)}
- G06F 13/4291: {using a clocked protocol}
- G06F 13/4295: {using an embedded synchronisation}
- G06F 16/60: of audio data
- H03K 3/0377: {Bistables with hysteresis, e.g. Schmitt trigger (non-regenerative amplitude discriminators G01R19/165)}
- H03K 5/086: {generated by feedback}
- H04J 3/0638: {Clock or time synchronisation among nodes; Internode synchronisation (synchronization for ring networks H04L12/422; data switching networks with synchronous transmission H04L12/43)}
- H04J 3/0647: {Synchronisation among TDM nodes}
- H04L 7/0008: {Synchronisation information channels, e.g. clock distribution lines}
- H04L 12/40006: {Architecture of a communication node (current supply arrangements H04L12/10; intermediate storage or scheduling H04L49/90)}
- H03K 5/2481: {with at least one differential stage}
- H04J 3/0652: {Synchronisation among time division multiple access [TDMA] nodes, e.g. time triggered protocol [TTP] (bus network with centralized control in which slots are of a TDMA packet structure H04L12/4035)}
- H04L 7/033: using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H04J: MULTIPLEX COMMUNICATION (transmission in general H04B; peculiar to transmission of digital information H04L5/00; systems for the simultaneous or sequential transmission of more than one television signal H04N7/08; in exchanges H04Q11/00; stereophonic systems H04S)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

A method is described and in one embodiment includes detecting a transition of a data signal comprising a data packet received at a circuit while the circuit is in a first hysteresis mode; placing the circuit in a second hysteresis mode subsequent to the detecting; and returning the receiver to the first hysteresis mode subsequent to completion of receipt of the data packet to await receipt of a next data packet. In certain embodiments, the first hysteresis mode is a high hysteresis mode and the second hysteresis mode is a standard hysteresis mode. In some embodiments, a level of each of the first and second hysteresis modes is dynamically tunable.

## Claims

### Claim 1

A method comprising:
detecting a transition of a data signal comprising a data packet received at a circuit while the circuit is in a first hysteresis mode;
placing the circuit in a second hysteresis mode subsequent to the detecting; and
returning the circuit to the first hysteresis mode subsequent to completion of receipt of the data packet to await receipt of a next data packet;
wherein the circuit comprises a comparator and wherein the returning the circuit to the first hysteresis mode comprises dynamically decreasing a number of devices comprising a feedback circuit of the comparator.

### Claim 2 (depends on 1)

The method of claim 1, wherein the first hysteresis mode is a high hysteresis mode and the second hysteresis mode is a standard hysteresis mode.

### Claim 3 (depends on 1)

The method of claim 1, wherein a level of each of the first and second hysteresis modes is dynamically tunable.

### Claim 4 (depends on 1)

The method of claim 1, wherein the completion of receipt of the data packet is indicated by deactivation of a receiver enable signal.

### Claim 5 (depends on 1)

The method of claim 1, wherein the transition comprises a LOW to HIGH transition of the data signal.

### Claim 6 (depends on 1)

The method of claim 1, wherein the transition comprises a HIGH to LOW transition of the data signal.

### Claim 7 (depends on 1)

The method of claim 1, wherein the transition comprises a first edge of the data packet.

### Claim 8 (depends on 1)

The method of claim 1, wherein the transition comprises an Nth transition of the data signal.

### Claim 9 (depends on 1)

The method of claim 1, wherein circuit comprises a comparator and wherein the placing the circuit in the second hysteresis mode comprises dynamically increasing a number of devices comprising a feedback circuit of the comparator.

### Claim 10

An apparatus comprising:
first circuitry for detecting a transition of a data signal comprising a data packet received at a circuit while the circuit is in a first hysteresis mode;
second circuitry for placing the circuit in a second hysteresis mode subsequent to the detecting; and
third circuitry for returning the circuit to the first hysteresis mode subsequent to completion of receipt of the data packet to await a next data packet;
wherein the circuit comprises a comparator and wherein the placing the circuit in the second hysteresis mode comprises dynamically increasing a number of devices comprising a feedback circuit of the comparator.

### Claim 11 (depends on 10)

The apparatus of claim 10, wherein the first hysteresis mode is a high hysteresis mode and the second hysteresis mode is a standard hysteresis mode and wherein a level of each of the first and second hysteresis modes is dynamically tunable.

### Claim 12 (depends on 10)

The apparatus of claim 10, wherein the transition comprises one of a LOW to HIGH transition and a HIGH to LOW transition.

### Claim 13 (depends on 10)

The apparatus of claim 10, wherein the transition comprises a first edge of the data packet.

### Claim 14 (depends on 10)

The apparatus of claim 10, wherein the transition comprises an Nth transition of the data signal.

### Claim 15 (depends on 10)

The apparatus of claim 10, wherein the circuit comprises a comparator and wherein the returning the circuit to the first hysteresis mode comprises dynamically decreasing a number of devices comprising a feedback circuit of the comparator.

### Claim 16 (depends on 10)

The apparatus of claim 10 wherein the comparator comprises:
a comparator core; and
a plurality of pairs of cross-coupled devices, wherein a number of the cross-coupled devices connected to provide a feedback circuit for the comparator core is dynamically controllable to control a hysteresis level of the comparator.

### Claim 17 (depends on 16)

The apparatus of claim 16, wherein the number of the cross-coupled devices connected to provide a feedback circuit for the comparator core is dynamically controllable via a control current.

### Claim 18

A method comprising:
detecting a transition of a data signal comprising a data packet received at a circuit while the circuit is in a first hysteresis mode;
placing the circuit in a second hysteresis mode subsequent to the detecting; and
returning the circuit to the first hysteresis mode subsequent to completion of receipt of the data packet to await receipt of a next data packet;
wherein circuit comprises a comparator and wherein the placing the circuit in the second hysteresis mode comprises dynamically increasing a number of devices comprising a feedback circuit of the comparator.

### Claim 19 (depends on 18)

The method of claim 18, wherein a level of each of the first and second hysteresis modes is dynamically tunable.

### Claim 20 (depends on 18)

The method of claim 18, wherein the transition comprises an Nth transition of the data signal.