# US 10,374,580 B2 · FIR filter circuit design method using approximate computing

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- Number: US 10,374,580 B2
- Document ID: US10374580B2
- Status: Granted
- Kind: B2
- Application number: 15/883,104
- Filed: 2018-01-30
- Published: 2018-08-09
- Granted: 2019-08-06
- Earliest claimed: 2017-02-06
- Assignees: Unist(Uslan National Institute of Science and Technology)
- Applicants: Unist(Ulsan National Institute of Science and Technology)
- Inventors: Seokhyeong Kang; Yesung Kang
- Web page: https://patentgrep.com/patent/US10374580B2

## CPC

- H03H 17/0238: {Measures concerning the arithmetic used (performing computations G06F7/60)}
- H03H 17/0223: {Computation saving measures; Accelerating measures (computations per se G06F)}
- H03H 17/06: Non-recursive filters
- H03H 2017/0081: {of FIR filters}
- H03H 2017/0245: {Measures to reduce power consumption}
- H03H: IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS (waveguides, resonators, lines or other devices of the waveguide type H01P)

## Abstract

A finite impulse response (FIR) filter circuit design method using approximate computing, the FIR filter circuit design method including: replacing adders of the FIR filter with approximate adders; and performing a synthesis work according to a set approximate synthesis flow when the replacing of the adders of the FIR filter are replaced with the approximate adders is performed, wherein, in the approximate synthesis flow, a numeric column of each of the approximate adders is divided into an accurate part and an inaccurate part, and a numeric column of the inaccurate part is approximated. In the FIR filter, conventional adders/subtractors are replaced with addition/subtraction having an automated synthesis flow so that energy consumption can be reduced.

## Claims

### Claim 1

A finite impulse response (FIR) filter circuit design method using approximate computing, the FIR filter circuit design method comprising:
replacing adders of a FIR filter with approximate adders; and
performing a synthesis work according to a set approximate synthesis flow when the replacing of the adders of the FIR filter are replaced with the approximate adders is performed,
wherein, in the set approximate synthesis flow, the approximate adders are divided into an accurate part and an inaccurate part, and the inaccurate part is approximated,
wherein the synthesis work according to the set approximate synthesis flow comprises:
classifying adders;
initializing a number of approximate bits of the classified adders;
synthesizing the adders to calculate sensitivity and accuracy;
comparing designs of the FIR filter to one another through calculation of sensitivity and accuracy, and designating iteration of a design having largest sensitivity as a seed of a next iteration; and
comparing the sensitivity with a set value and determining an updated sensitivity.

### Claim 2 (depends on 1)

The FIR filter circuit design method of claim 1, wherein, in the set approximate synthesis flow, the accuracy is defined by Equation 1:
accuracy
=
min
k
=
1
,
⁢
…
⁢
,
M
⁢
(
1
-

result
k
-
ref
k


ref
k

)
×
100
⁢
%
,
(
1
)
where resultk is an approximate result generated from a k-th input pattern, and refk is a correct result.

### Claim 3 (depends on 1)

The FIR filter circuit design method of claim 1, wherein, in the set approximate synthesis flow, the sensitivity is defined by a sensitivity factor (SF) which is defined by Equation 2:
S
⁢
⁢
F
=
{
accuracy
-
accuracy
min
delay
,
if
⁢
⁢
accuracy
>
accuracy
min
0
,
else
.
(
2
)

### Claim 4 (depends on 1)

The FIR filter circuit design method of claim 1, wherein, in the set approximate synthesis flow, to verify an output quality of a processed image, peak signal-to-noise-ratio (PSNR) is defined by Equation 3:
PSNR
=
10
×
log
⁡
(
255
2
σ
noise
2
)
,
(
3
)
where σnoise2 is a variance of a difference.

### Claim 5 (depends on 1)

The FIR filter circuit design method of claim 1, wherein the initializing of the number of approximate bits of the classified adders comprises initializing the number of approximate bits of the classified adders as “0”.

### Claim 6 (depends on 1)

The FIR filter circuit design method of claim 1, wherein the comparing of the sensitivity with a set value and determining of the sensitivity comprises, when the sensitivity is smaller than 0, performing an operation of calculating sensitivity and accuracy by synthesizing the adders, again.

### Claim 7 (depends on 1)

The FIR filter circuit design method of claim 1, wherein the synthesizing of the adders comprises:
increasing the number of approximate bits of the adders in a first step by 1;
checking maximum operating frequency through synthesis;
checking accuracy through simulation; and
calculating sensitivity with respect to a variance of the number of approximate bits.