# US 10,374,574 B2 · Method of providing protective cavity and integrated passive components in wafer level chip scale package using a carrier wafer > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,374,574 B2 - Document ID: US10374574B2 - Status: Granted - Kind: B2 - Application number: 15/371,315 - Filed: 2016-12-07 - Published: 2017-06-08 - Granted: 2019-08-06 - Earliest claimed: 2015-12-08 - Assignees: Skyworks Solutions, Inc. - Applicants: Skyworks Solutions, Inc. - Inventors: Joseph Michael Bulger - Web page: https://patentgrep.com/patent/US10374574B2 ## CPC - H03H 9/0576: {including surface acoustic wave [SAW] devices} - H03H 3/08: for the manufacture of resonators or networks using surface acoustic waves - H03H 9/0538: {Constructional combinations of supports or holders with electromechanical or other electronic elements} - H03H 9/1007: {for bulk acoustic wave [BAW] devices} - H03H 9/1057: {for microelectro-mechanical devices} - H03H 9/1071: {the enclosure being defined by a frame built on a substrate and a cap, the frame having no mechanical contact with the SAW device} - H10N 30/01: Manufacture or treatment - H03H: IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS (waveguides, resonators, lines or other devices of the waveguide type H01P) - H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR ## Abstract A wafer-level chip-scale package includes a body, a conductive via passing through the body, a contact bump formed at a lower portion of the body and in electrical connection with a lower end of the conductive via, a piezoelectric substrate directly bonded to an upper end of the conductive via, and a cavity defined between a portion of the body and the piezoelectric substrate. ## Claims ### Claim 1 A wafer-level chip-scale package comprising: a polymeric body having a conductive via passing through the polymeric body and a contact bump formed at a lower portion of the polymeric body and in electrical connection with a lower end of the conductive via; a piezoelectric substrate directly bonded to an upper end of the conductive via with one of a transient liquid phase bond and a solder bond, the wafer-level chip-scale package having a cavity defined between a portion of the polymeric body and the piezoelectric substrate; and a seal ring including metal disposed in the body and having an upper end directly bonded to the piezoelectric substrate. ### Claim 2 (depends on 1) The wafer-level chip-scale package of claim 1 further comprising a metal roof encapsulated in a dielectric and disposed on an upper surface of the body below the cavity. ### Claim 3 (depends on 2) The wafer-level chip-scale package of claim 2 further comprising metal standoffs disposed between the dielectric and the piezoelectric substrate. ### Claim 4 (depends on 1) The wafer-level chip-scale package of claim 1 further comprising a metal standoff disposed between one of the upper end of the conductive via and the piezoelectric substrate and the upper end of the seal ring and the piezoelectric substrate. ### Claim 5 (depends on 1) The wafer-level chip-scale package of claim 1 wherein the seal ring surrounds the cavity and hermetically seals the cavity. ### Claim 6 (depends on 1) The wafer-level chip-scale package of claim 1 further comprising a dielectric layer disposed on walls of the cavity and hermetically sealing the cavity. ### Claim 7 (depends on 1) The wafer-level chip-scale package of claim 1 further comprising interdigital (IDT) electrodes of an acoustic wave filter disposed on the piezoelectric substrate within the cavity. ### Claim 8 (depends on 1) The wafer-level chip-scale package of claim 1 further comprising a passive device disposed within the body. ### Claim 9 (depends on 8) The wafer-level chip-scale package of claim 8 wherein the passive device includes an inductor. ### Claim 10 (depends on 1) The wafer-level chip-scale package of claim 1 wherein the body includes polyimide. ### Claim 11 (depends on 10) The wafer-level chip-scale package of claim 10 wherein the body includes two layers of polymer and a dielectric layer disposed between the two layers of polymer. ### Claim 12 (depends on 1) The wafer-level chip-scale package of claim 1 further comprising a first polymer standoff disposed between the body and the piezoelectric substrate. ### Claim 13 (depends on 12) The wafer-level chip-scale package of claim 12 wherein the first polymer standoff defines a first lateral end of the cavity and a second polymer standoff disposed between the body and the piezoelectric substrate defines a second lateral end of the cavity. ### Claim 14 (depends on 1) The wafer-level chip-scale package of claim 1 further comprising a metal roof disposed within the body below the cavity. ### Claim 15 (depends on 1) The wafer-level chip-scale package of claim 1 further comprising a metal roof disposed on an upper surface of the body and defining a lower surface of the cavity. ### Claim 16 (depends on 15) The wafer-level chip-scale package of claim 15 further comprising metal standoffs disposed between the metal roof and the piezoelectric substrate. ### Claim 17 (depends on 1) The wafer-level chip-scale package of claim 1 included in an electronic device module. ### Claim 18 (depends on 17) The wafer-level chip-scale package of claim 17 wherein the electronic device module is a radio frequency (RF) device module. ### Claim 19 (depends on 18) The wafer-level chip-scale package of claim 18 wherein the electronic device module is included in a duplexer. ### Claim 20 (depends on 18) The wafer-level chip-scale package of claim 18 included in an electronic device. ### Claim 21 (depends on 20) The wafer-level chip-scale package of claim 20 wherein the electronic device is an RF device. ### Claim 22 A wafer-level chip-scale package comprising: a polymeric body having a conductive via passing through the polymeric body and a contact bump formed at a lower portion of the polymeric body and in electrical connection with a lower end of the conductive via; a piezoelectric substrate directly bonded to an upper end of the conductive via with one of a transient liquid phase bond and a solder bond, the wafer-level chip-scale package having a cavity defined between a portion of the polymeric body and the piezoelectric substrate; a metal roof disposed on an upper surface of the body and defining a lower surface of the cavity; and metal standoffs disposed between the metal roof and the piezoelectric substrate. ### Claim 23 A wafer-level chip-scale package comprising: a polymeric body including polyimide having a conductive via passing through the polymeric body and a contact bump formed at a lower portion of the polymeric body and in electrical connection with a lower end of the conductive via, the body including two layers of polymer and a dielectric layer disposed between the two layers of polymer; and a piezoelectric substrate directly bonded to an upper end of the conductive via with one of a transient liquid phase bond and a solder bond, the wafer-level chip-scale package having a cavity defined between a portion of the polymeric body and the piezoelectric substrate. ### Claim 24 A wafer-level chip-scale package comprising: a polymeric body having a conductive via passing through the polymeric body and a contact bump formed at a lower portion of the polymeric body and in electrical connection with a lower end of the conductive via; a piezoelectric substrate directly bonded to an upper end of the conductive via with one of a transient liquid phase bond and a solder bond, the wafer-level chip-scale package having a cavity defined between a portion of the polymeric body and the piezoelectric substrate; a metal roof encapsulated in a dielectric and disposed on an upper surface of the body below the cavity; and metal standoffs disposed between the dielectric and the piezoelectric substrate.