# US 10,374,440 B2 · System and method for supercapacitor charging and balancing > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,374,440 B2 - Document ID: US10374440B2 - Status: Granted - Kind: B2 - Application number: 15/630,172 - Filed: 2017-06-22 - Published: 2018-12-27 - Granted: 2019-08-06 - Earliest claimed: 2017-06-22 - Assignees: Rockwell Collins, Inc. - Applicants: Rockwell Collins, Inc. - Inventors: George Altemose - Web page: https://patentgrep.com/patent/US10374440B2 ## CPC - H02J 7/52: for charge balancing, e.g. equalisation of charge between batteries - H02J 7/54: Passive balancing, e.g. using resistors or parallel MOSFETs - H02J 7/56: Active balancing, e.g. using capacitor-based, inductor-based or DC-DC converters - H02J 7/82: Control of state of charge [SOC] - H01G 11/00: Hybrid capacitors, i.e. capacitors having different positive and negative electrodes; Electric double-layer [EDL] capacitors; Processes for the manufacture thereof or of parts thereof - H01G 11/14: Arrangements or processes for adjusting or protecting hybrid or EDL capacitors (emergency protective circuit arrangements specially adapted for capacitors, and effecting automatic switching in the event of an undesired change from normal working conditions H02H7/16; emergency protective circuit arrangements for limiting excess current or voltages without disconnection H02H9/00) - H02J 2207/50: Charging of capacitors, supercapacitors, ultra-capacitors or double layer capacitors - Y02E 60/13: Energy storage using capacitors - H02J: ELECTRIC POWER NETWORKS; CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY - H01G: CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE (selection of specified materials as dielectric H01B3/00; capacitors having potential barriers H10D1/62, H10K10/10) - Y02E: REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION ## Abstract In an illustrative embodiment, a supercapacitor system includes a common bus and a number of supercapacitor units, each of the supercapacitor units including one or more supercapacitors, coupled to the common bus via a balancing circuit, where each balancing circuit is configured to balance a charge of the one or more supercapacitors in the supercapacitor units by conducting current to supercapacitor units with a lower charge from supercapacitor units with a higher charge over the common bus, each balancing circuit including at least a first switch and a second switch, each switch controlled by a clock signal. ## Claims ### Claim 1 A supercapacitor system, comprising: a DC power supply; a clock generator, the clock generator including: an oscillator circuit; a counter which receives a clock input signal from the oscillator circuit; a first D type flip flop coupled to the counter; and a second D type flip flop coupled to the counter, wherein the output of the first D type flip flop is fed to a first buffer and provides the first phase of the clock signal and the second D type flip flop is fed to a second buffer and provides the second phase of the clock signal; a DC common bus; and a plurality of supercapacitor units, wherein all of the plurality of supercapacitor units are electrically coupled in series, each of the plurality of supercapacitor units including one or more supercapacitors, coupled to the DC common bus via a balancing circuit, wherein the balancing circuit is configured to balance a charge of the one or more supercapacitors in the plurality of supercapacitor units by conducting current to supercapacitor units with a lower charge from supercapacitor units with a higher charge over the DC common bus, the DC power supply coupled directly to the DC common bus, and the balancing circuit includes at least a first switch and a second switch, each switch controlled by a clock signal provided by the clock generator, the clock generator configured to provide a first phase of the clock signal for the first switch which does not overlap a second phase of the clock signal from the second switch. ### Claim 2 (depends on 1) The supercapacitor system of claim 1, wherein the first switch and the second switch are MOSFET transistors. ### Claim 3 (depends on 1) The supercapacitor system of claim 1, wherein the first switch and the second switch are bipolar junction transistors. ### Claim 4 (depends on 1) The supercapacitor system of claim 1, wherein each balancing circuit of the plurality of supercapacitor units is capacitively coupled to the DC common bus. ### Claim 5 (depends on 1) The supercapacitor system of claim 1, wherein each balancing circuit of the plurality of supercapacitor units is coupled to the DC common bus via a transformer. ### Claim 6 (depends on 1) The supercapacitor system of claim 1, wherein the DC charger power supply has a maximum voltage equal to a rated voltage of the one or more supercapacitors in the plurality of supercapacitor units. ### Claim 7 (depends on 1) The supercapacitor system of claim 1, wherein the each of the plurality of supercapacitor units further includes a housing, the housing being configured to contain the one or more supercapacitors and the supercapacitor balancing circuit. ### Claim 8 (depends on 1) The supercapacitor system of claim 1, wherein the one or more supercapacitors in each of the plurality of supercapacitors are electrically coupled in parallel to form a virtual supercapacitor. ### Claim 9 (depends on 1) The supercapacitor system of claim 1, wherein each supercapacitor balancing circuit of plurality of supercapacitor units is configured to allow current to flow over the DC common bus from supercapacitor units with a higher charge to supercapacitor units with a lower charge until all of the supercapacitor units have the same charge. ### Claim 10 (depends on 1) The supercapacitor system of claim 1, wherein the counter is a four-bit octal johnson counter. ### Claim 11 (depends on 1) The supercapacitor system of claim 1, wherein the output of the first D type flip flop is coupled to a reset of the second D type flip flop and the output of the second D type flip flop is coupled to a reset of the first D type flip flop to ensure the first phase of the clock signal does not overlap the second phase of the clock signal. ### Claim 12 (depends on 1) The supercapacitor system of claim 1, wherein the clock input signal is approximately 800 kHZ.