# US 10,374,419 B2 · Distributed electrostatic discharge protection for an on-package input/output architecture

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- Number: US 10,374,419 B2
- Document ID: US10374419B2
- Status: Granted
- Kind: B2
- Application number: 15/043,370
- Filed: 2016-02-12
- Published: 2016-06-09
- Granted: 2019-08-06
- Earliest claimed: 2016-02-12
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Todd W. Mellinger; Michael E. Griffith; Ganesh Balamurugan; Thomas P. Thomas
- Web page: https://patentgrep.com/patent/US10374419B2

## CPC

- H02H 9/046: {responsive to excess voltage appearing at terminals of integrated circuits}
- G06F 1/16: Constructional details or arrangements
- G06F 1/1613: {for portable computers (cooling arrangements therefor G06F1/203; constructional details or arrangements for pocket calculators, electronic agendas or books G06F15/0216; constructional details of portable telephone sets: with several bodies H04M1/0202)}
- H03K 19/00361: {in field effect transistor circuits}
- H10D 89/611: {using diodes as protective elements}
- H02H: EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS (indicating or signalling undesired working conditions G01R, e.g. G01R31/00, G08B; locating faults along lines G01R31/08; emergency protective devices H01H)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

An on-package interface. A first set of single-ended transmitter circuits on a first die. A first set of single-ended receiver circuits on a second die. The receiver circuits have a termination circuit comprising an inverter and a resistive feedback element. A plurality of conductive lines couple the first set of transmitter circuits and the first set of receiver circuits. The lengths of the plurality of conductive lines are matched.

## Claims

### Claim 1

An apparatus, comprising:
circuitry on a semiconductor chip to drive a signal externally from said semiconductor chip, said circuitry comprising:
a) a first driver slice having a first series resistance coupled to an output pad of the semiconductor chip;
b) a second driver slice having a second series resistance coupled to the output pad, the second series resistance having a different designed-for resistance than said first series resistance;
c) electrostatic discharge (ESD) protection diodes directly coupled to the output pad.

### Claim 2 (depends on 1)

The apparatus of claim 1 wherein said signal is one of a plurality of signals to be respectively driven over a plurality of equal length signal traces from said semiconductor chip to a second semiconductor chip.

### Claim 3 (depends on 2)

The apparatus of claim 2 wherein none of said equal length signal traces are coupled to an equalization circuit.

### Claim 4 (depends on 1)

The apparatus of claim 1 wherein said semiconductor chip is within a multi-chip package.

### Claim 5 (depends on 1)

The apparatus of claim 1 wherein said semiconductor chip comprises a processor.

### Claim 6 (depends on 1)

The apparatus of claim 1 wherein said semiconductor chip comprises a memory.

### Claim 7 (depends on 1)

The apparatus of claim 1 wherein said semiconductor chip is a component in a computing system.

### Claim 8 (depends on 7)

The apparatus of claim 7 wherein said computing system comprises any of:
a) sensors;
b) a network interface.

### Claim 9 (depends on 1)

The apparatus of claim 1 wherein said semiconductor chip resides within a computing system.