# US 10,374,389 B2 · Plasmonic mode III-V laser as on-chip light source > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,374,389 B2 - Document ID: US10374389B2 - Status: Granted - Kind: B2 - Application number: 15/474,534 - Filed: 2017-03-30 - Published: 2018-09-20 - Granted: 2019-08-06 - Earliest claimed: 2015-11-13 - Assignees: International Business Machines Corporation; The George Washington University - Applicants: International Business Machines Corporation; The George Washington University - Inventors: Ning Li; Ke Liu; Devendra K. Sadana; Volker J. Sorger - Web page: https://patentgrep.com/patent/US10374389B2 ## CPC - G02B 6/12004: {Combinations of two or more optical elements} - G02B 6/12002: {Three-dimensional structures} - G02B 6/1226: {involving surface plasmon interaction} - G02B 6/136: by etching - G02B 6/43: Arrangements comprising a plurality of opto-electronic elements and associated optical interconnections - H01S 5/04252: {characterised by the material} - H01S 5/1046: {Comprising interactions between photons and plasmons, e.g. by a corrugated surface} - H01S 5/34346: {characterised by the materials of the barrier layers} - H01S 5/021: {Silicon based substrates} - H01S 5/026: Monolithically integrated components, e.g. waveguides, monitoring photo-detectors, drivers (stabilisation of output H01S5/06) - H01S 5/1042: {Optical microcavities, e.g. cavity dimensions comparable to the wavelength} - H01S 5/3401: {having no PN junction, e.g. unipolar lasers, intersubband lasers, quantum cascade lasers} - G02B: OPTICAL ELEMENTS, SYSTEMS OR APPARATUS - H01S: DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL ## Abstract A plasmonic light source includes a substrate and a square nano-cavity formed on the substrate. The nano-cavity includes a quantum well structure. The quantum well structure includes III-V materials. A plasmonic metal is formed as an electrode on the square nano-cavity and is configured to excite surface plasmons with the quantum well structure to generate light. Complementary metal oxide semiconductor (CMOS) devices are formed on the substrate. ## Claims ### Claim 1 A plasmonic light source, comprising: a nano-cavity quantum well structure including III-V materials disposed on a contact layer formed on a complementary metal oxide semiconductor (CMOS) substrate; and a plasmonic metal formed as an electrode on the nano-cavity and configured to excite surface plasmons with the quantum well structure to generate light to form a nano-cavity light source with low parasitic capacitance. ### Claim 2 (depends on 1) The light source as recited in claim 1, further comprising a waveguide disposed adjacent to and spaced apart from the nano-cavity and configured to couple plasmonic light from the nano-cavity. ### Claim 3 (depends on 1) The light source as recited in claim 1, further comprising a waveguide and the nano-cavity being disposed in-line within the waveguide and configured to couple plasmonic light from the nano-cavity. ### Claim 4 (depends on 3) The light source as recited in claim 3, wherein the plasmonic metal is disposed transversely to a longitudinal direction of the waveguide and extends beyond the nano-cavity and the waveguide on at least one side of the nano-cavity and the waveguide. ### Claim 5 (depends on 1) The light source as recited in claim 1, wherein the quantum well structure is sandwiched between buffer layers. ### Claim 6 (depends on 1) The light source as recited in claim 1, wherein the plasmonic metal is compatible with CMOS processing. ### Claim 7 (depends on 1) The light source as recited in claim 1, wherein the plasmonic light source includes an operating temperature compatible with the CMOS devices on a same chip. ### Claim 8 (depends on 1) The light source as recited in claim 1, wherein the plasmonic light source includes one of a laser or a light emitting diode. ### Claim 9 (depends on 1) The light source as recited in claim 1, wherein the nano-cavity include a square shape in a top down view. ### Claim 10 A method for forming an on-chip plasmonic light source, comprising: oxide wafer bonding a quantum well structure formed on a III-V substrate with an oxide formed on a silicon substrate; removing the III-V substrate to transfer the quantum well structure to the silicon substrate; and forming a plasmonic metal as an electrode on the quantum well structure to form a nano-cavity light source. ### Claim 11 (depends on 10) The method as recited in claim 10, further comprising forming a waveguide disposed adjacent to and spaced apart from the nano-cavity. ### Claim 12 (depends on 11) The method as recited in claim 11, further comprising forming a waveguide with the nano-cavity light source being disposed in-line within the waveguide. ### Claim 13 (depends on 12) The method as recited in claim 12, wherein the plasmonic metal is disposed transversely to a longitudinal direction of the waveguide and extends beyond the nano-cavity and the waveguide on at least one side of the nano-cavity and the waveguide. ### Claim 14 (depends on 10) The method as recited in claim 10, further comprising patterning the quantum well structure to form a square nano-cavity light source on the silicon substrate. ### Claim 15 (depends on 1) The light source as recited in claim 1, further including an oxide formed on the quantum well structure and oxide wafer bonded to the substrate. ### Claim 16 (depends on 5) The light source as recited in claim 5, wherein a bottom buffer layer of the buffer layers includes a portion extending beyond the quantum well structure and has an electrode formed on the portion. ### Claim 17 (depends on 5) The light source as recited in claim 5, wherein a top buffer layer of the buffer layers operates as a contact layer to provide a conductive path between the plasmonic metal and the quantum well structure. ### Claim 18 (depends on 10) The method as recited in claim 10, further including forming a top buffer layer on the quantum well structure to provide a contact layer as a conductive path between the plasmonic metal and the quantum well structure. ### Claim 19 (depends on 10) The method as recited in claim 10, further including forming a bottom buffer layer on the quantum well structure between the quantum well structure and the silicon substrate. ### Claim 20 (depends on 19) The method as recited in claim 19, wherein the bottom buffer layer includes a portion extending beyond the quantum well structure and has an electrode formed on the portion.