# US 10,374,154 B1 · Methods of shielding an embedded MRAM array on an integrated circuit product comprising CMOS based transistors > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,374,154 B1 - Document ID: US10374154B1 - Status: Granted - Kind: B1 - Application number: 15/874,205 - Filed: 2018-01-18 - Published: 2019-07-18 - Granted: 2019-08-06 - Earliest claimed: 2018-01-18 - Assignees: Globalfoundries Inc. - Applicants: GLOBALFOUNDRIES Singapore Pte Ltd - Inventors: Dimitri Houssameddine; Chenchen Jacob Wang; Bin Liu - Web page: https://patentgrep.com/patent/US10374154B1 ## CPC - H10N 50/01: Manufacture or treatment - H10B 61/22: {of the field-effect transistor [FET] type} - H10N 50/10: Magnetoresistive devices - H10P 95/94: {Hydrogenation or deuterisation, e.g. using atomic hydrogen from a plasma} - H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR - H10B: ELECTRONIC MEMORY DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract One illustrative method disclosed herein includes forming an MRAM memory array and a plurality of peripheral circuits for an integrated circuit product above a semiconductor substrate, forming a patterned layer of a metal-containing shielding material above the substrate, the patterned layer of metal-containing shielding material covering the MRAM memory array while leaving an area above the plurality of peripheral circuits exposed, and, with the patterned layer of metal-containing shielding material in position, performing a silicon dangling bond passivation anneal process on the integrated circuit product. ## Claims ### Claim 1 A method of forming an integrated circuit product, comprising: forming an MRAM memory array and a plurality of peripheral circuits for said integrated circuit product above a semiconductor substrate; forming a patterned layer of a metal-containing shielding material above said semiconductor substrate, said patterned layer of metal-containing shielding material covering said MRAM memory array while leaving an area above said plurality of peripheral circuits exposed; and with said patterned layer of metal-containing shielding material in position, performing a silicon dangling bond passivation anneal process on said integrated circuit product. ### Claim 2 (depends on 1) The method of claim 1, further comprising removing said patterned layer of metal-containing shielding material. ### Claim 3 (depends on 1) The method of claim 1, wherein forming said patterned layer of metal-containing shielding material comprises: blanket-depositing a continuous layer of metal-containing shielding material above said semiconductor substrate; forming a patterned etch mask above said continuous layer of metal-containing shielding material, said patterned etch mask covering a first portion of said continuous layer of metal-containing shielding material positioned above said MRAM memory array while exposing a second portion of said continuous layer of metal-containing shielding material above said plurality of peripheral circuits; and with said patterned etch mask in position, performing at least one etching process to remove said exposed second portion of said continuous layer of metal-containing shielding material so as to thereby form said patterned layer of metal-containing shielding material. ### Claim 4 (depends on 3) The method of claim 3, further comprising removing said patterned etch mask prior to performing said silicon dangling bond passivation anneal process. ### Claim 5 (depends on 1) The method of claim 1, wherein performing said silicon dangling bond passivation anneal process comprises performing said silicon dangling bond passivation anneal process in an ambient comprising hydrogen (H2) and deuterium (D2). ### Claim 6 (depends on 1) The method of claim 1, wherein said patterned layer of metal-containing shielding material comprises one of a metal, a metal alloy, a metal oxide, tungsten, tantalum, ruthenium, platinum or aluminum and wherein said patterned layer of metal-containing shielding material has a thickness that falls within a range of about 10-1000 nm. ### Claim 7 (depends on 1) The method of claim 1, wherein said patterned layer of metal-containing material is electrically conductive. ### Claim 8 (depends on 1) The method of claim 1, wherein said patterned layer of metal-containing material comprises at least 30% metal (atomic percentage). ### Claim 9 (depends on 1) The method of claim 1, wherein forming said MRAM memory array comprises forming a plurality of MRAM cells for said MRAM memory array and forming said plurality of peripheral circuits comprises forming a plurality of logic circuits. ### Claim 10 (depends on 9) The method of claim 9, wherein each of said MRAM cells comprises: a bottom electrode; a top electrode; and a MTJ (Magnetic Tunnel Junction) element positioned above said bottom electrode and below said top electrode. ### Claim 11 (depends on 10) The method of claim 10, wherein said MTJ element comprises a first pinned ferromagnetic material layer positioned above said bottom electrode, a second free ferromagnetic material layer positioned below said top electrode and a tunnel barrier layer positioned above said first pinned ferromagnetic material layer and below said second free ferromagnetic material layer. ### Claim 12 (depends on 11) The method of claim 11, wherein forming said MRAM memory array further comprises forming a plurality of read-switching transistors, wherein each of said read-switching transistors is conductively coupled to only one of said plurality of MRAM cells in said MRAM memory array. ### Claim 13 A method of forming an integrated circuit product, comprising: forming an MRAM memory array and a plurality of peripheral circuits for said integrated circuit product above a semiconductor substrate; forming a patterned layer of a shielding insulating material above said semiconductor substrate, said patterned layer of shielding insulating material covering said MRAM memory array while leaving an area above said plurality of peripheral circuits exposed; and with said patterned layer of shielding insulating material in position, performing a silicon dangling bond passivation anneal process on said integrated circuit product. ### Claim 14 (depends on 13) The method of claim 13, wherein forming said patterned layer of shielding insulating material comprises: blanket-depositing a continuous layer of said shielding insulating material above said semiconductor substrate; forming a patterned etch mask above said continuous layer of shielding insulating material, said patterned etch mask covering a first portion of said continuous layer of shielding insulating material positioned above said MRAM memory array while exposing a second portion of said continuous layer of shielding insulating material above said plurality of peripheral circuits; and with said patterned etch mask in position, performing at least one etching process to remove said exposed second portion of said continuous layer of shielding insulating material so as to thereby form said patterned layer of shielding insulating material. ### Claim 15 (depends on 13) The method of claim 13, wherein performing said silicon dangling bond passivation anneal process comprises performing said silicon dangling bond passivation anneal process to passivate dangling silicon bonds present in a plurality of CMOS based transistors formed for said plurality of peripheral circuits. ### Claim 16 (depends on 13) The method of claim 13, wherein forming said plurality of peripheral circuits comprises forming a plurality of logic circuits and wherein forming said MRAM memory array comprises forming a plurality of read-switching transistors, wherein each of said read-switching transistors is conductively coupled to only one of said plurality of MRAM cells in said MRAM memory array.