# US 10,374,152 B2 · Magnetic tunnel junction based anti-fuses with cascoded transistors

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- Number: US 10,374,152 B2
- Document ID: US10374152B2
- Status: Granted
- Kind: B2
- Application number: 15/231,168
- Filed: 2016-08-08
- Published: 2017-06-22
- Granted: 2019-08-06
- Earliest claimed: 2015-12-22
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Anthony J. Annunziata; John K. DeBrosse; Chandrasekharan Kothandaraman
- Web page: https://patentgrep.com/patent/US10374152B2

## CPC

- H10N 50/01: Manufacture or treatment
- G11C 11/161: {details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell}
- G11C 11/1659: {Cell access}
- G11C 11/1673: {Reading or sensing circuits or methods}
- G11C 11/1675: {Writing or programming circuits or methods}
- G11C 17/165: {Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses (digital stores using resistance random access memory elements G11C13/0002)}
- H10B 61/22: {of the field-effect transistor [FET] type}
- H10N 50/80: Constructional details
- H10W 20/491: {Antifuses, i.e. interconnections changeable from non-conductive to conductive}
- H10N 50/10: Magnetoresistive devices
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Magnetic tunnel junction antifuse devices are protected from degradation caused by programming voltage drop across the gates of unselected magnetic tunnel junction antifuses by connecting said magnetic tunnel junctions serially with a first field effect transistor and a second field effect transistor, the first field effect transistor having its gate connected to a positive supply voltage while the gate of the second field effect transistor is switchably connected to a programming voltage, such that when the second field effect transistor of a selected magnetic tunnel junction is switched to direct the programming voltage to program the selected magnetic tunnel junction an unswitched magnetic tunnel junction and the second field effect transistor do not experience a voltage drop across the gates thereof sufficient to degrade.

## Claims

### Claim 1

A method for protecting an unselected magnetic tunnel junction in an array of magnetic tunnel junctions from being accidentally blown by antifuse programming voltage applied to a selected magnetic tunnel junction wired in parallel therewith, the method comprising:
connecting said selected magnetic tunnel junction serially with a first field effect transistor and a second field effect transistor, the first field effect transistor having its gate connected to an unswitchable positive supply voltage while the gate of the second field effect transistor is switchably connected to a programming voltage of 1.5 to 2 volts;
connecting a first electrode of the selected magnetic tunnel junction to a bias line and connecting a second electrode of the selected magnetic tunnel junction to an electrode of the first field effect transistor;
switching the second field effect transistor of the selected magnetic tunnel junction to direct the programming voltage to program the selected magnetic tunnel junction while the unselected magnetic tunnel junction is unswitched, and the unswitched magnetic tunnel junction and the second field effect transistor do not experience a voltage drop across the gates thereof sufficient to degrade an oxide of a transistor associated with the unswitched magnetic tunnel junction; and
wherein the selected magnetic tunnel junction has a resistance of 10 kΩ to 20 kΩ prior to application of the programming voltage and wherein the selected magnetic tunnel junction, upon application of the programming voltage, is shorted across a tunnel dielectric layer so as to have a resistance of 10 Ω to 1 kΩ.

### Claim 2 (depends on 1)

The method of claim 1, wherein the programming voltage is from 1.5 to 2 volts.

### Claim 3 (depends on 1)

The method of claim 1, wherein the programming voltage is approximately 1.8 volts.

### Claim 4 (depends on 1)

The method of claim 1, wherein the positive supply voltage is from 200 millivolts to 300 millivolts.

### Claim 5 (depends on 1)

The method of claim 1, wherein the positive supply voltage is from 200 millivolts to 300 millivolts.

### Claim 6 (depends on 1)

The method of claim 1, wherein the array of magnetic tunnel junctions comprises a plurality of magnetic tunnel junctions; and further comprising connecting a portion of said plurality of magnetic tunnel junctions each serially with a first field effect transistor and a second field effect transistor, the first field effect transistor having its gate connected to a positive supply voltage while the gate of the second field effect transistor is switchably connected to a programming voltage, such that less than the total number of said plurality of magnetic tunnel junctions in the array are connected serially with a first field effect transistor and a second field effect transistor.

### Claim 7 (depends on 6)

The method of claim 6, further comprising connecting a decoder circuit to the second field effect transistors such that application of a programmed voltage can result in selective application of the programming voltage of one or more of the plurality of magnetic tunnel junctions thereby shorting one or more of the plurality of magnetic tunnel junctions.

### Claim 8 (depends on 6)

The method of claim 6, further comprising connecting a logic circuit to the plurality of magnetic tunnel junctions that selectively disables or enables portions of a device based upon the shorting of one or more of the plurality of magnetic tunnel junctions.

### Claim 9 (depends on 1)

The method of claim 1, wherein a bias line voltage is approximately 1 volt.

### Claim 10 (depends on 1)

The method of claim 1, wherein a bias line voltage is approximately 1 volt.

### Claim 11 (depends on 1)

The method of claim 1, wherein the magnetic tunnel junction is comprised of a reference layer, a tunnel barrier layer and a free layer.

### Claim 12 (depends on 11)

The method of claim 11, wherein the reference layer has a thickness of 5 to 25 nm.

### Claim 13 (depends on 11)

The method of claim 11, wherein the free layer has a thickness of 5 to 25 nm.

### Claim 14

A method for reducing degradation caused by a programming voltage across a gate drain junction of a magnetic tunnel junction in an array of magnetic tunnel junctions wired in parallel, the method comprising:
connecting the magnetic tunnel junction serially with a first field effect transistor and a second field effect transistor such that a first electrode of the magnetic tunnel junction is connected to a bias line and a second electrode of the magnetic tunnel junction is connected to an electrode of the first field effect transistor;
connecting a gate of the first field effect transistor to an unswitchable positive supply voltage such that a voltage drop across the gate of the first field effect transistor is not sufficient to degrade an oxide of a transistor associated with an unswitched magnetic tunnel junction; and
switchably connecting a gate of the second field effect transistor to the programming voltage such that a voltage drop across the gate of the second field effect transistor is not sufficient to degrade an oxide of the transistor associated with the unswitched magnetic tunnel junction;
wherein the magnetic tunnel junction has a resistance of 10 kΩ to 20 kΩ prior to application of the programming voltage and wherein the magnetic tunnel junction, upon application of the programming voltage, is shorted across a tunnel dielectric layer so as to have a resistance of 10 kΩ to 1 kΩ.

### Claim 15 (depends on 14)

The method of claim 14, wherein the programming voltage is approximately 1.8 volts.

### Claim 16 (depends on 14)

The method of claim 14, wherein the positive supply voltage is from 200 millivolts to 300 millivolts.

### Claim 17 (depends on 14)

The method of claim 14, wherein the programming voltage is from 1.5 to 2 volts and wherein the positive supply voltage is from 200 millivolts to 300 millivolts.