# US 10,374,129 B2 · Compound semiconductors having an improved high temperature resistant backside metallization

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- Number: US 10,374,129 B2
- Document ID: US10374129B2
- Status: Granted
- Kind: B2
- Application number: 15/813,596
- Filed: 2017-11-15
- Published: 2019-03-28
- Granted: 2019-08-06
- Earliest claimed: 2017-09-26
- Assignees: Win Semiconductors Corp.
- Applicants: WIN Semiconductors Corp.
- Inventors: Chang-Hwang Hua; Shu Chen Chen; Huang-Wen Wang; Walter Tony Wohlmuth
- Web page: https://patentgrep.com/patent/US10374129B2

## CPC

- H10H 20/8312: {extending at least partially through the bodies}
- H10H 20/8316: {Multi-layer electrodes comprising at least one discontinuous layer}
- H10H 20/85: Packages
- H10H 20/8506: {Containers}
- H10P 14/6506: {Formation of intermediate materials}
- H10P 95/904: {of Group III-V semiconductors}
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/0234: {comprising etching via holes that stop on pads or on electrodes}
- H10W 20/0242: {comprising etching via holes from the back sides of the chips, wafers or substrates}
- H10W 20/0261: {characterised by the filling method or the material of the conductive fill}
- H10W 20/043: {for electroplating}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 70/095: {of vias therein}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 72/01355: {by use of masks}
- H10W 72/01935: {by plating, e.g. electroless plating or electroplating}
- H10W 72/0198: {batch processes}
- H10W 72/07336: {Soldering or alloying}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/331: {Shapes of die-attach connectors}
- H10W 72/352: {comprising metals or metalloids, e.g. solders}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/922: {Bond pads being integral with underlying chip-level interconnections}
- H10W 72/9223: {with redistribution layers [RDL]}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/934: {Cross-sectional shape, i.e. in side view}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10H: INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

An improved high temperature resistant backside metallization for compound semiconductors comprises a front-side metal layer formed on a compound semiconductor substrate; at least one via hole penetrating the compound semiconductor substrate, a top of an inner surface of the via hole is defined by the front-side metal layer; at least one seed metal layer, at least one backside metal layer and at least one diffusion barrier layer sequentially formed on a bottom surface of the compound semiconductor substrate and the inner surface of the via hole, the seed metal layer and the front-side metal layer are electrically connected through the via hole; a die attachment metal layer formed on a bottom surface of the diffusion barrier layer other than the via hole and an adjacent area near the via hole. The diffusion barrier layer prevents the backside metal layer from diffusing into the die attachment metal layer.

## Claims

### Claim 1

Compound semiconductors having an improved high temperature resistant backside metallization comprises:
a compound semiconductor substrate;
a front-side metal layer formed on a top surface of said compound semiconductor substrate;
at least one substrate via hole, wherein each of said at least one substrate via hole penetrates said compound semiconductor substrate, wherein each of said at least one substrate via hole has an inner surface having a top defined by said front-side metal layer;
at least one seed metal layer formed on a bottom surface of said compound semiconductor substrate and said inner surface of each of said at least one substrate via hole, wherein said at least one seed metal layer and said front-side metal layer are electrically connected through said at least one substrate via hole;
at least one backside metal layer formed on an outer surface of said at least one seed metal layer, wherein a peripheral area of said outer surface of said at least one seed metal layer is not covered by said at least one backside metal layer;
at least one diffusion barrier layer formed on an outer surface of said at least one backside metal layer; and
a die attachment metal layer foil led on a bottom surface of said at least one diffusion barrier layer other than said at least one substrate via hole and other than an adjacent area near each of said at least one substrate via hole;
thereby said at least one diffusion barrier layer prevents said at least one backside metal layer from diffusing into said die attachment metal layer.

### Claim 2 (depends on 1)

The compound semiconductors having an improved high temperature resistant backside metallization according to claim 1, wherein each of said at least one diffusion barrier layer is made of at least one material selected from the group consisting of: Ni or Ni alloy, Vanadium or Vanadium alloy, and Pd.

### Claim 3 (depends on 2)

The compound semiconductors having an improved high temperature resistant backside metallization according to claim 2, wherein each of said at least one diffusion barrier layer is made of NiV.

### Claim 4 (depends on 1)

The compound semiconductors having an improved high temperature resistant backside metallization according to claim 1, wherein said compound semiconductor substrate is made of one material selected from the group consisting of: GaAs, SiC, GaN, sapphire and InP.

### Claim 5 (depends on 1)

The compound semiconductors having an improved high temperature resistant backside metallization according to claim 1, wherein each of said at least one seed metal layer is made of at least one material selected from the group consisting of: Pd, Ti and TiW.

### Claim 6 (depends on 1)

The compound semiconductors having an improved high temperature resistant backside metallization according to claim 1, wherein each of said at least one backside metal layer is made of at least one material selected from the group consisting of: Au and Au alloy.

### Claim 7 (depends on 1)

The compound semiconductors having an improved high temperature resistant backside metallization according to claim 1, wherein said die attachment metal layer is made of one material selected from the group consisting of: Sn and Sn alloy.

### Claim 8 (depends on 7)

The compound semiconductors having an improved high temperature resistant backside metallization according to claim 7, wherein said die attachment metal layer is made of AuSn alloy.

### Claim 9 (depends on 8)

The compound semiconductors having an improved high temperature resistant backside metallization according to claim 8, wherein the AuSn alloy has 80 percent Au by weight and 20 percent Sn by weight.

### Claim 10 (depends on 1)

The compound semiconductors having an improved high temperature resistant backside metallization according to claim 1, wherein said at least one diffusion barrier layer has a thickness greater than or equal to 1000 Å and less than or equal to 20000 Å.

### Claim 11 (depends on 1)

The compound semiconductors having an improved high temperature resistant backside metallization according to claim 1, wherein said at least one seed metal layer has a thickness greater than or equal to 100 Å and less than or equal to 10000 Å.

### Claim 12 (depends on 1)

The compound semiconductors having an improved high temperature resistant backside metallization according to claim 1, wherein said die attachment metal layer has a thickness greater than or equal to 5 μm and less than or equal to 20 μm.

### Claim 13 (depends on 1)

The compound semiconductors having an improved high temperature resistant backside metallization according to claim 1, wherein said at least one backside metal layer has a thickness greater than or equal to 1 μm and less than or equal to 10 μm.

### Claim 14 (depends on 1)

The compound semiconductors having an improved high temperature resistant backside metallization according to claim 1, wherein said compound semiconductor substrate is made of one material selected from the group consisting of: SiC, GaN and sapphire, wherein each of said at least one seed metal layer is made of one material selected from the group consisting of: Ti and TiW alloy.

### Claim 15 (depends on 1)

The compound semiconductors having an improved high temperature resistant backside metallization according to claim 1, wherein said compound semiconductor substrate is made of one material selected from the group consisting of: GaAs and InP, wherein each of said at least one seed metal layer is made of one material selected from the group consisting of: Pd, Ti and TiW.