# US 10,374,103 B1 · Crystallized silicon vertical diode on BEOL for access device for confined PCM arrays

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- Number: US 10,374,103 B1
- Document ID: US10374103B1
- Status: Granted
- Kind: B1
- Application number: 15/938,705
- Filed: 2018-03-28
- Granted: 2019-08-06
- Earliest claimed: 2018-03-28
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Fabio Carta; Chung H. Lam; Matthew J. BrightSky; Bahman Hekmatshoartabari
- Web page: https://patentgrep.com/patent/US10374103B1

## CPC

- H10B 63/20: {comprising selection components having two electrodes, e.g. diodes}
- H10B 63/82: {the switching components having a common active material layer}
- H10D 8/60: Schottky-barrier diodes
- H10P 14/2905: {Silicon, silicon germanium or germanium}
- H10P 14/3802: {Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth}
- H10D 8/00: Diodes (variable-capacitance diodes H10D1/64; gated diodes H10D12/00)
- H10D 8/01: Manufacture or treatment
- H10D 8/045: {of PN junction diodes}
- H10D 8/50: PIN diodes
- H10N 70/231: {based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect}
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3816: {Pulsed laser beam}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

A method is presented for integrating an electronic component in back end of the line (BEOL) processing. The method includes forming a first electrode over a semiconductor substrate, forming a first electrically conductive material over a portion of the first electrode, and forming a second electrically conductive material over the first electrically conductive material, where the first and second electrically conductive materials define a p-n junction. The method further includes depositing a second electrode between a set of spacers and in direct contact with the p-n-junction, depositing a phase change material over the p-n junction and in direct contact with the second electrode, and forming a third electrode over a portion of the phase change material.

## Claims

### Claim 1

A method for integrating an electronic component in back end of the line (BEOL) processing, the method comprising:
forming a first electrode over a semiconductor substrate;
forming a first electrically conductive material over a portion of the first electrode;
forming a second electrically conductive material over the first electrically conductive material, where the first and second electrically conductive materials define a p-n junction;
depositing a second electrode between a set of spacers and in direct contact with the p-n-junction;
depositing a phase change material over the p-n junction and in direct contact with the second electrode; and
forming a third electrode over a portion of the phase change material.

### Claim 2 (depends on 1)

The method of claim 1, wherein the first electrically conductive material is an n-type poly-silicon layer.

### Claim 3 (depends on 2)

The method of claim 2, wherein second electrically conductive material is a p-type poly-silicon layer.

### Claim 4 (depends on 1)

The method of claim 1, further comprising forming the p-n junction and the second electrode between interlayer dielectric (ILD) regions.

### Claim 5 (depends on 1)

The method of claim 1, wherein the phase change material extends a length of the first electrode.

### Claim 6 (depends on 1)

The method of claim 1, wherein the electronic component is a poly-silicon diode.

### Claim 7 (depends on 1)

The method of claim 1, wherein the p-n junction is an access device and the phase change material is a memory element, the access device combined with the memory element to be positioned between a plurality of first and third electrodes defining a crosspoint array.

### Claim 8

A method for integrating an electronic component in back end of the line (BEOL) processing, the method comprising:
forming a first electrode over a semiconductor substrate;
forming a first electrically conductive material over the first electrode;
forming an undoped intrinsic semiconductor layer over the first electrically conductive material;
forming a second electrically conductive material over the undoped intrinsic semiconductor layer, where the first electrically conductive material, the undoped intrinsic semiconductor layer, and the second electrically conductive material define a p-i-n junction;
depositing a second electrode between a set of spacers and in direct contact with the p-i-n-junction;
depositing a phase change material over t p-i-n junction and in direct contact with the second electrode; and
forming a third electrode over a portion of the phase change material.

### Claim 9 (depends on 8)

The method of claim 8, wherein the first electrically conductive material is an n-type poly-silicon layer.

### Claim 10 (depends on 9)

The method of claim 9, wherein second electrically conductive material is a p-type poly-silicon layer.

### Claim 11 (depends on 8)

The method of claim 8, further comprising forming the p-i-n junction and the second electrode between interlayer dielectric (ILD) regions.

### Claim 12 (depends on 8)

The method of claim 8, wherein the phase change material extends a length of the first electrode and a length of the first electrically conductive material.

### Claim 13 (depends on 8)

The method of claim 8, wherein the electronic component is a poly-silicon diode.

### Claim 14 (depends on 8)

The method of claim 8, wherein the p-i-n junction is an access device and the phase change material is a memory element, the access device combined with the memory element to be positioned between a plurality of first and third electrodes defining a crosspoint array.

### Claim 15

A semiconductor structure for integrating an electronic component in back end of the line (BEOL) processing, the structure comprising:
a first electrode disposed over a semiconductor substrate;
a first electrically conductive material disposed over a portion of the first electrode;
a second electrically conductive material disposed over the first electrically conductive material, where the first and second electrically conductive materials define a p-n junction;
a second electrode located between a set of spacers and in direct contact with the p-n-junction;
a phase change material located over the p-n junction and in direct contact with the second electrode; and
a third electrode disposed over a portion of the phase change material.

### Claim 16 (depends on 15)

The semiconductor structure of claim 15, wherein the first electrically conductive material is an n-type poly-silicon layer.

### Claim 17 (depends on 16)

The semiconductor structure of claim 16, wherein second electrically conductive material is a p-type poly-silicon layer.

### Claim 18 (depends on 15)

The semiconductor structure of claim 15, wherein the p-n junction and the second electrode are disposed between interlayer dielectric (ILD) regions.

### Claim 19 (depends on 15)

The semiconductor structure of claim 15, wherein the phase change material extends a length of the first electrode.

### Claim 20 (depends on 15)

The semiconductor structure of claim 15, wherein the electronic component is a poly-silicon diode.