# US 10,374,102 B2 · Semiconductor device

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- Number: US 10,374,102 B2
- Document ID: US10374102B2
- Status: Granted
- Kind: B2
- Application number: 15/889,098
- Filed: 2018-02-05
- Published: 2018-06-21
- Granted: 2019-08-06
- Earliest claimed: 2013-03-25
- Assignees: Fuji Electric Co., Ltd.
- Applicants: Fuji Electric Co., Ltd.
- Inventors: Yuichi Onozawa; Takashi Yoshimura; Hiroshi Takishita
- Web page: https://patentgrep.com/patent/US10374102B2

## CPC

- H10D 8/60: Schottky-barrier diodes
- H10D 8/051: {of Schottky diodes}
- H10D 8/411: {PN diodes having planar bodies}
- H10D 12/441: {Vertical IGBTs}
- H10D 62/106: {having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions}
- H10D 62/107: {Buried supplementary regions, e.g. buried guard rings (multi-RESURF H10D62/111)}
- H10D 62/129: {Cathode regions of diodes}
- H10D 62/53: the imperfections being within the semiconductor body
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/208: {of electrically inactive species}
- H10P 32/14: within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase
- H10P 32/1406: {by ion implantation}
- H10P 32/171: {being group IV material}
- H10P 32/18: {Diffusion lifetime killers}
- H10P 34/40: with high-energy radiation
- H10P 52/00: Grinding, lapping or polishing of wafers, substrates or parts of devices
- H10P 95/90: Thermal treatments, e.g. annealing or sintering
- H10D 8/043: {of planar diodes}
- H10D 62/108: {having localised breakdown regions, e.g. built-in avalanching regions (in self-protected thyristors H10D18/211)}
- H10D 62/60: Impurity distributions or concentrations
- H10P 34/42: with electromagnetic radiation, e.g. laser annealing (laser cutting H10P54/20)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes first to fourth semiconductor regions, and first and second electrodes. The second semiconductor region is selectively disposed in a surface layer of one main surface of the first semiconductor region. The first electrode is in contact with a contact region of the second semiconductor region. The third semiconductor region is disposed in a surface layer on another main surface of the first semiconductor region, and having an impurity concentration higher than that of the first semiconductor region. The second electrode is in contact with the third semiconductor region. The fourth semiconductor region of the second conductivity type is disposed in the first semiconductor region, and disposed closer to the one main surface than the third semiconductor region. The fourth semiconductor region is disposed at least within the contact region in a plan view.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate;
a first semiconductor region of a first conductivity type, in the substrate;
a second semiconductor region of a second conductivity type, in the substrate, the second semiconductor region being selectively disposed in a surface layer of one main surface of the first semiconductor region, the second semiconductor region having a contact region;
a first electrode in contact with the contact region of the second semiconductor region;
a third semiconductor region of the first conductivity type disposed in a surface layer on another main surface of the first semiconductor region, the third semiconductor region having an impurity concentration higher than an impurity concentration of the first semiconductor region;
a plurality of fourth semiconductor regions of the second conductivity type disposed in the first semiconductor region, the fourth semiconductor regions being disposed closer to the one main surface than is the third semiconductor region, the fourth semiconductor regions being disposed inside and outside the contact region in a plan view of the semiconductor device, the fourth semiconductor regions extending in a direction parallel to the another main surface and being spaced from each other;
a second electrode in contact with the third semiconductor region; and
a fifth semiconductor region of the first conductivity type, the fifth semiconductor region having an impurity concentration higher than the impurity concentration of the first semiconductor region and lower than the impurity concentration of the third semiconductor region, the fifth semiconductor region being disposed in the first semiconductor region, and being closer to the one main surface than is each of the fourth semiconductor regions, the fifth semiconductor region having a Schottky junction contacting the second electrode.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein an occupation area ratio of a surface area of the plurality of fourth semiconductor regions to a surface area of an active region in which a main current flows is equal to or greater than 90% and no greater than 98%.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein one of the fourth semiconductor regions has a length in a direction parallel to the another main surface equal to or greater than 250 μm.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, wherein the semiconductor device satisfies
L1≥{(q·μ·d·Np·Vbi)/J}1/2
where L1 is a length of one of the fourth semiconductor regions in a direction parallel to the one surface, J is a current density of a main current that flows through an active region, q is an elementary charge, μ is hole mobility, d is a thickness of the one of the fourth semiconductor regions in a depth direction, Np is an impurity concentration of the fourth semiconductor regions, and Vbi is a built-in potential of a pn junction between the one of the fourth semiconductor regions and the third semiconductor region.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, wherein the distance between the outermost periphery of the contact region and the outermost periphery of one of the fourth semiconductor regions in the plan view is equal to or less than 2000 μm.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1, wherein
the first semiconductor region has a rectangular shape with a first side in a first direction and a second side in second direction perpendicular to the first direction, in the plan view,
one of the fourth semiconductor regions has a shape with a third side that is parallel to the first side and a fourth side that is parallel to the second side.

### Claim 7 (depends on 1)

The semiconductor device according to claim 1, wherein the outermost periphery of one of the fourth semiconductor regions is located inside of the third semiconductor region in the plan view.

### Claim 8

A semiconductor device, comprising
a substrate;
a first semiconductor region of a first conductivity type, in the substrate;
a second semiconductor region of a second conductivity type, in the substrate, the second semiconductor region being selectively disposed in a surface layer of one main surface of the first semiconductor region, the second semiconductor region having a contact region;
a first electrode in contact with the contact region of the second semiconductor region;
a third semiconductor region of the first conductivity type disposed in a surface layer on another main surface of the first semiconductor region, the third semiconductor region having an impurity concentration higher than an impurity concentration of the first semiconductor region;
a plurality of fourth semiconductor regions of the second conductivity type disposed in the first semiconductor region, the fourth semiconductor regions being disposed closer to the one main surface than is the third semiconductor region, the fourth semiconductor regions being disposed inside and outside the contact region in a plan view of the semiconductor device, the fourth semiconductor regions extending in a direction parallel to the another main surface and being spaced from each other by gaps, the plurality of fourth semiconductor regions including
a plurality of first fourth semiconductor regions, each of which is disposed inside of the contact region, and
a plurality of second fourth semiconductor regions, each of which is disposed outside of the contact region; and
a second electrode in contact with the third semiconductor region, wherein
the semiconductor device includes first to fourth areas in the plan view,
the first area being outside of the contact region, and having an area size A20,
the second area being a total area of surfaces of the second fourth semiconductor regions, and having an area size A21 in total,
the third area being inside of the contact region, and having an area size A10,
the fourth area being a total area of surfaces of the first fourth semiconductor regions and having an area size A11 in total, and
the area sizes A20, A21, A10 and A11 satisfy A21/A20<A11/A10.

### Claim 9 (depends on 8)

The semiconductor device according to claim 8, wherein each gap between two adjacent ones of the plurality of second fourth semiconductor regions is greater than each gap between two adjacent ones of the plurality of first fourth semiconductor regions.

### Claim 10

A semiconductor device, comprising:
a substrate;
a first semiconductor region of a first conductivity type, in the substrate;
a second semiconductor region of a second conductivity type, in the substrate, the second semiconductor region being selectively disposed in a surface layer of one main surface of the first semiconductor region, the second semiconductor region having a contact region;
a first electrode in contact with the contact region of the second semiconductor region;
a third semiconductor region of the first conductivity type disposed in a surface layer on another main surface of the first semiconductor region, the third semiconductor region having an impurity concentration higher than an impurity concentration of the first semiconductor region;
a fourth semiconductor region of the second conductivity type disposed in the first semiconductor region, the fourth semiconductor region being disposed closer to the one main surface than is the third semiconductor region, the fourth semiconductor region being disposed at least within the contact region in a plan view of the semiconductor device; and
a second electrode in contact with the third semiconductor region, wherein
a distance between an outermost periphery of the contact region and an outermost periphery of the fourth semiconductor region within the contact region in the plan view is equal to or greater than a diffusion length of a minority carrier.

### Claim 11

A semiconductor device, comprising:
a substrate;
a first semiconductor region of a first conductivity type, in the substrate;
a second semiconductor region of a second conductivity type, in the substrate, the second semiconductor region being selectively disposed in a surface layer of one main surface of the first semiconductor region, the second semiconductor region having a contact region;
a first electrode in contact with the contact region of the second semiconductor region;
a third semiconductor region of the first conductivity type disposed in a surface layer on another main surface of the first semiconductor region, the third semiconductor region having an impurity concentration higher than an impurity concentration of the first semiconductor region;
a fourth semiconductor region of the second conductivity type disposed in the first semiconductor region, the fourth semiconductor region being disposed closer to the one main surface than is the third semiconductor region, the fourth semiconductor region being disposed at least within the contact region in a plan view of the semiconductor device;
a second electrode in contact with the third semiconductor region; and
a fifth semiconductor region of the first conductivity type, the fifth semiconductor region having an impurity concentration higher than the impurity concentration of the first semiconductor region and lower than the impurity concentration of the third semiconductor region, the fifth semiconductor region being disposed in the first semiconductor region, and being closer to the one main surface than is the fourth semiconductor region, wherein
an outermost periphery of the third semiconductor region is located further inside of the semiconductor device than is an outermost periphery of the first semiconductor region in the plan view, and
the fifth semiconductor region contacts the second electrode outside of the third semiconductor region in the plan view.

### Claim 12 (depends on 11)

The semiconductor device according to claim 11, further comprising an edge termination structure portion that encloses the active region and holds a breakdown voltage, wherein
the fourth semiconductor region is disposed in the active region, and
the active region has an avalanche breakdown voltage lower than an avalanche breakdown voltage of the edge terminal structure portion.

### Claim 13

A semiconductor device, comprising:
a substrate;
a first semiconductor region of a first conductivity type, in the substrate;
a second semiconductor region of a second conductivity type, in the substrate, the second semiconductor region being selectively disposed in a surface layer of one main surface of the first semiconductor region, the second semiconductor region having a contact region;
a first electrode in contact with the contact region of the second semiconductor region;
a third semiconductor region of the first conductivity type disposed in a surface layer on another main surface of the first semiconductor region, the third semiconductor region having an impurity concentration higher than an impurity concentration of the first semiconductor region;
a fourth semiconductor region of the second conductivity type disposed in the first semiconductor region, the fourth semiconductor region being disposed closer to the one main surface than is the third semiconductor region, the fourth semiconductor region being disposed at least within the contact region in a plan view of the semiconductor device;
a second electrode in contact with the third semiconductor region; and
a fifth semiconductor region of the first conductivity type, the fifth semiconductor region having an impurity concentration higher than the impurity concentration of the first semiconductor region and lower than the impurity concentration of the third semiconductor region, the fifth semiconductor region being disposed in the first semiconductor region, and being closer to the one main surface than is the fourth semiconductor region; and
a sixth semiconductor region of the second conductivity type disposed in the fifth semiconductor region, the sixth semiconductor region being disposed outside of the third semiconductor region in the plan view, and being spaced from each of the third semiconductor region and the fourth semiconductor region.

### Claim 14

A semiconductor device, comprising:
a substrate;
a first semiconductor region of a first conductivity type, in the substrate;
a second semiconductor region of a second conductivity type, in the substrate, the second semiconductor region being selectively disposed in a surface layer of one main surface of the first semiconductor region, the second semiconductor region having a contact region;
a first electrode in contact with the contact region of the second semiconductor region;
a third semiconductor region of the first conductivity type disposed in a surface layer on another main surface of the first semiconductor region, the third semiconductor region having an impurity concentration higher than an impurity concentration of the first semiconductor region;
a fourth semiconductor region of the second conductivity type disposed in the first semiconductor region, the fourth semiconductor region being disposed closer to the one main surface than is the third semiconductor region, the fourth semiconductor region being disposed at least within the contact region in a plan view of the semiconductor device;
a second electrode in contact with the third semiconductor region; and
a fifth semiconductor region of the first conductivity type, the fifth semiconductor region having an impurity concentration higher than the impurity concentration of the first semiconductor region and lower than the impurity concentration of the third semiconductor region, the fifth semiconductor region being disposed in the first semiconductor region, and being closer to the one main surface than is the fourth semiconductor region, wherein
the fifth semiconductor region is formed by a plurality of proton irradiation processes, and includes a plurality of fifth semiconductor regions, at least one of the fifth semiconductor regions having a depth different from a depth of another one of the fifth semiconductor regions, relative to the another main surface.

### Claim 15 (depends on 14)

The semiconductor device according to claim 14, wherein the fifth semiconductor regions are disposed closer to the one main surface than is the fourth semiconductor region and away from the fourth semiconductor region.

### Claim 16

A semiconductor device, comprising:
a substrate;
a first semiconductor region of a first conductivity type, in the substrate;
a second semiconductor region of a second conductivity type, in the substrate, the second semiconductor region being selectively disposed in a surface layer of one main surface of the first semiconductor region, the second semiconductor region having a contact region;
a first electrode in contact with the contact region of the second semiconductor region;
a third semiconductor region of the first conductivity type disposed in a surface layer on another main surface of the first semiconductor region, the third semiconductor region having an impurity concentration higher than an impurity concentration of the first semiconductor region;
a fourth semiconductor region of the second conductivity type disposed in the first semiconductor region, the fourth semiconductor region being disposed closer to the one main surface than is the third semiconductor region, the fourth semiconductor region being disposed at least within the contact region in a plan view of the semiconductor device;
a second electrode in contact with the third semiconductor region;
an edge termination structure portion; and
an active region in which a main current flows and that keeps a voltage thereof lower than a breakdown voltage, the active region being enclosed by the edge termination structure portion, wherein
the fourth semiconductor region is disposed in the active region, and
the active region has an avalanche breakdown voltage lower than an avalanche breakdown voltage of the edge terminal structure portion.

### Claim 17

A semiconductor device, comprising:
a substrate;
a first semiconductor region of a first conductivity type, in the substrate;
a second semiconductor region of a second conductivity type, in the substrate, the second semiconductor region being selectively disposed in a surface layer of one main surface of the first semiconductor region, the second semiconductor region having a contact region;
a first electrode in contact with the contact region of the second semiconductor region;
a third semiconductor region of the first conductivity type disposed in a surface layer on another main surface of the first semiconductor region, the third semiconductor region having an impurity concentration higher than an impurity concentration of the first semiconductor region;
a fourth semiconductor region of the second conductivity type disposed in the first semiconductor region, the fourth semiconductor region being disposed closer to the one main surface than is the third semiconductor region, the fourth semiconductor region being disposed at least within the contact region in a plan view;
a second electrode in contact with the third semiconductor region; and
a solder layer disposed on the second electrode at a side opposite to the third semiconductor region so that the semiconductor device is bonded to an other element through the solder layer and the second electrode, the solder layer covering at least a portion of a side surface of the first semiconductor region from the second electrode.