# US 10,374,100 B2 · Programmable non-volatile memory with low off current

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- Number: US 10,374,100 B2
- Document ID: US10374100B2
- Status: Granted
- Kind: B2
- Application number: 15/637,986
- Filed: 2017-06-29
- Published: 2019-01-03
- Granted: 2019-08-06
- Earliest claimed: 2017-06-29
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Doug Weiser; Jack G. Qian
- Web page: https://patentgrep.com/patent/US10374100B2

## CPC

- H10D 30/68: Floating-gate IGFETs
- H10B 41/00: Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B 41/30: characterised by the memory core region
- H10D 30/022: {having lightly-doped source or drain extensions selectively formed at the sides of the gates}
- H10D 30/0411: {of FETs having floating gates}
- H10D 30/637: {Lateral IGFETs having no inversion channels, e.g. buried channel lateral IGFETs, normally-on lateral IGFETs or depletion-mode lateral IGFETs}
- H10D 30/6891: {characterised by the shapes, relative sizes or dispositions of the floating gate electrode}
- H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures}
- H10D 84/0128: {Manufacturing their channels}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P 30/222: {characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

In one disclosed embodiment, a non-volatile memory cell is constructed using a floating gate transistor with a channel that includes a buried channel region interposed between two surface channel regions under a floating gate. The surface channel regions are formed using angled lightly-doped drain implantation at locations in the substrate so that a first surface channel region is located under a first end of the floating gate and a second surface channel region is located under a second end of the floating gate. In one embodiment, the floating gate transistor is a PMOS transistor, with the channel being formed in an n-well formed in a p-type substrate, with the buried channel region being formed using a Vtp implant, and with the surface channel regions being formed using angled NLDD implants. The surface channel regions increase the energy barrier along the channel and reduce off state current of the memory cell.

## Claims

### Claim 1

A method for fabricating a non-volatile memory comprising:
forming a buried channel region in a substrate;
forming a gate dielectric layer over the substrate;
forming a floating gate over the gate dielectric layer;
forming a first surface channel region under a first end of the floating gate;
forming a second surface channel region under a second end of the floating gate opposite the first end; and
forming a source and a drain in the substrate.

### Claim 2 (depends on 1)

The method as claimed in claim 1, wherein after forming the first and second surface channel regions, the buried channel region is interposed between the first and second surface channel regions under the floating gate.

### Claim 3 (depends on 1)

The method as claimed in claim 1, wherein the first surface channel region and the second surface channel region are formed by performing a lightly doped drain (LDD) implant.

### Claim 4 (depends on 3)

The method as claimed in claim 3, wherein the LDD implant that forms the first surface channel region and the second surface channel region is performed at an angle of less than 90 degrees with respect to the surface of the substrate on which the gate dielectric layer is formed.

### Claim 5 (depends on 4)

The method as claimed in claim 4, wherein the angle is approximately 45 degrees.

### Claim 6 (depends on 1)

The method as claimed in claim 1, wherein the non-volatile memory comprises a PMOS floating gate transistor, the substrate is a p-type substrate, and forming the buried channel region in the p-type substrate comprises:
forming an n-well in the p-type substrate by performing an n-type dopant implant; and
forming the buried channel region in the n-well by performing a p-channel threshold voltage (Vtp) implant.

### Claim 7 (depends on 6)

The method as claimed in claim 6, wherein the Vtp implant comprises at least one of boron and phosphorus.

### Claim 8 (depends on 6)

The method as claimed in claim 6, wherein the LDD implant that forms the first surface channel region and the second surface channel region is an n-type light doped drain (NLDD) implant.

### Claim 9 (depends on 8)

The method as claimed in claim 8, wherein the NLDD implant forming the first surface channel region and the second surface channel region is performed at an angle of less than 90 degrees with respect to the surface of the p-type substrate on which the gate dielectric layer is formed.

### Claim 10 (depends on 9)

The method as claimed in claim 9, wherein the NLDD implant is performed at a first angle to form the first surface channel region and at a second angle to form the second surface channel region, wherein the first and second angles are each between approximately 30 and 60 degrees with respect to the surface of the p-type substrate on which the gate dielectric layer is formed.

### Claim 11 (depends on 10)

The method as claimed in claim 10, wherein the first and second angles are different.

### Claim 12 (depends on 8)

The method as claimed in claim 8, wherein the NLDD implant comprises phosphorus.

### Claim 13 (depends on 6)

The method as claimed in claim 6, wherein forming the source and the drain in the p-type substrate comprises:
forming first and second p-type lightly doped drain (PLDD) regions in the n-well by performing a PLDD implant, the first PLDD region being formed on a first side of the floating gate and the second PLDD region being formed on a second side of the floating gate;
forming first and second sidewall spacers over the gate dielectric layer, the first sidewall spacer being adjacent to the first end of the floating gate and the second sidewall spacer being adjacent to the second end of the floating gate; and
forming first and second p-type source drain (PSD) regions in the n-well by performing a PSD implant using the sidewall spacers as a mask, the first PSD region being formed on the first side of the floating gate and the second PSD region being formed on the second side of the floating gate, wherein the first PLDD region and first PSD region form the source and the second PLDD region and the second PSD region form the drain.

### Claim 14

A device comprising:
a non-volatile memory having a plurality of non-volatile memory cells, each non-volatile memory cell including a floating gate transistor comprising:
a substrate including a channel region formed between a source and a drain, wherein the channel region includes a buried channel region, a first surface channel region, and a second surface channel region, and wherein the buried channel portion is interposed between the first surface channel region and the second surface channel region; and
a floating gate disposed over the substrate and overlying the channel region.

### Claim 15 (depends on 14)

The device as claimed in claim 14, wherein the first surface channel region is located under a first end of the floating gate, the second surface channel region is located under a second end of the floating gate opposite the first end, and the buried channel region is located under a portion of the floating gate between the first and second ends.

### Claim 16 (depends on 14)

The device as claimed in claim 14, wherein:
the floating gate transistor is a PMOS floating gate transistor;
the substrate is a p-type substrate including an n-well region in which the channel region is formed;
the buried channel region includes a Vtp implant; and
the first and second surface channel regions include n-type lightly doped drain (NLDD) implants.

### Claim 17 (depends on 16)

The device as claimed in claim 16, wherein the non-volatile memory cell is a PMOS one time programmable (OTP) memory cell.

### Claim 18

A memory transistor comprising:
a substrate including a source, a drain, and a channel region extending between the source and the drain, wherein the channel region includes first and second surface channel regions at respective first and second ends of the channel region, the first surface channel region including a first lightly doped drain (LDD) implant region, and the second surface channel region including a second LDD implant region; and
a floating gate arranged over the substrate and overlying the channel region, wherein the LDD region is located under one of first and second opposite ends of the floating gate,
wherein the channel region includes a buried channel region located under the floating gate, the buried channel region being interposed between the first and second surface channel regions.

### Claim 19 (depends on 18)

The memory transistor as claimed in claim 18, wherein the second LDD region is located under the other of the first and second opposite ends of the floating gate.

### Claim 20 (depends on 18)

The memory transistor as claimed in claim 18, wherein the substrate is a p-type substrate, the LDD implant is an n-type LDD implant, and the buried channel region comprises a p-channel threshold voltage (Vtp) implant.