# US 10,374,099 B2 · Static random access memory (SRAM) device for improving electrical characteristics and logic device including the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,374,099 B2 - Document ID: US10374099B2 - Status: Granted - Kind: B2 - Application number: 15/911,148 - Filed: 2018-03-04 - Published: 2018-07-05 - Granted: 2019-08-06 - Earliest claimed: 2015-12-03 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Dong-hun Lee; Dong-won Kim - Web page: https://patentgrep.com/patent/US10374099B2 ## CPC - H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)} - G11C 11/419: Read-write [R-W] circuits - H10B 10/12: {comprising a MOSFET load element} - H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels} - H10D 30/024: {of fin field-effect transistors [FinFET]} - H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels} - H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around} - H10D 62/118: {Nanostructure semiconductor bodies} - H10D 62/119: {Nanowire, nanosheet or nanotube semiconductor bodies} - H10D 62/121: {oriented parallel to substrates} - H10D 62/213: {Channel regions of field-effect devices} - H10D 84/8311: {the IGFETs characterised by having different channel structures} - H10F 39/80377: {characterised by the channel of the transistor, e.g. channel having a doping gradient} - H10P 14/3462: {Nanowires} - H10P 14/3464: {Nanotubes} - H10B 43/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels - H10D 30/026: {having laterally-coplanar source and drain regions, a gate at the sides of the bulk channel, and both horizontal and vertical current flow (of LDMOS H10D30/0289)} - H10D 30/62: Fin field-effect transistors [FinFET] - H10D 62/292: {Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512)} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - G11C: STATIC STORES (semiconductor memory devices H10B) - H10B: ELECTRONIC MEMORY DEVICES - H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A static random access memory (SRAM) device includes a circuit element that includes a first inverter having a first load transistor and a first drive transistor and a second inverter having a second load transistor and a second drive transistor. Input and output nodes of the first inverter and the second inverter are cross-connected to each other. A first transfer transistor is connected to the output node of the first inverter, and a second transfer transistor is connected to the output nodes of the second inverter. Each of the first and second load transistors, the first and second drive transistors, and the first and second transfer transistors includes a transistor having multi-bridge channels. At least one of the first and second load transistors, the first and second drive transistors, and the first and second transfer transistors includes a transistor having a different number of multi-bridge channels from the other transistors. ## Claims ### Claim 1 A semiconductor device, comprising: a first inverter including a first load transistor and a first drive transistor; and a first transfer transistor connected to an output node of the first inverter, wherein the first load transistor includes a plurality of first multi-bridge channels, and a first source region and a first drain region on both sides of the first multi-bridge channels, the first drive transistor includes a plurality of second multi-bridge channels, and a second source region and a second drain region on both sides of the second multi-bridge channels, the first transfer transistor includes a plurality of third multi-bridge channels, and a third source region and a third drain region on both sides of the third multi-bridge channels, the number of the plurality of third multi-bridge channels is greater than the number of the plurality of first multi-bridge channels, and the first, the second and the third source and drain regions have a same height from a substrate. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein the number of the plurality of second multi-bridge channels is greater than the number of the plurality of first multi-bridge channels. ### Claim 3 (depends on 1) The semiconductor device of claim 1, wherein the number of the plurality of second multi-bridge channels is greater than the number of the plurality of third multi-bridge channels. ### Claim 4 (depends on 1) The semiconductor device of claim 1, wherein the first load transistor is a p-type metal oxide semiconductor (PMOS) transistor, and each of the first drive transistor and the first transfer transistor is an n-type metal oxide semiconductor (NMOS) transistor. ### Claim 5 (depends on 1) The semiconductor device of claim 1, wherein the semiconductor device is a static random access memory (SRAM) device. ### Claim 6 (depends on 1) The semiconductor device of claim 1, wherein each of the plurality of first, second and third multi-bridge channels includes a plurality of nano-bridges that are stacked on a semiconductor substrate and spaced apart from one another. ### Claim 7 (depends on 6) The semiconductor device of claim 6, wherein each of the plurality of nano-bridges has a rectangular sectional shape. ### Claim 8 (depends on 6) The semiconductor device of claim 6, wherein each of the plurality of nano-bridges has a quadrangular sectional shapes. ### Claim 9 (depends on 1) The semiconductor device of claim 1, further comprising: a second inverter including a second load transistor and a second drive transistor; and a second transfer transistor connected to an output node of the second inverter. ### Claim 10 A semiconductor device, comprising: a first inverter including a first load transistor and a first drive transistor; and a first transfer transistor connected to an output node of the first inverter, wherein the first load transistor includes a plurality of first multi-bridge channels, a first gate, and a first source region and a first drain region on both sides of the first gate and the first multi-bridge channels, the first drive transistor includes a plurality of second multi-bridge channels, a second gate extended from the first gate, and a second source region and a second drain region on both sides of the second gate and the second multi-bridge channels, the first transfer transistor includes a plurality of third multi-bridge channels, a third gate separated from the first and the second gates, and a third source region and a third drain region on both sides of the third gate and the third multi-bridge channels, the number of the plurality of third multi-bridge channels is greater than the number of the plurality of first multi-bridge channels, the first load transistor is a p-type metal oxide semiconductor (PMOS) transistor, each of the first drive transistor and the first transfer transistor is an n-type metal oxide semiconductor (NMOS) transistor, the first gate and the second gate are arranged in a first direction on a substrate, and the first multi-bridge channels are arranged in a second direction that is perpendicular to the first direction and between the first source region and the first drain region on the substrate, and the second multi-bridge channels are arranged in the second direction and between the second source region and the second drain region on the substrate, the third gate is arranged in the first direction on the substrate, and the third multi-bridge channels are arranged in the second direction and between the third source region and the third drain region on the substrate, and the first, the second and the third source and drain regions have a same height from the substrate. ### Claim 11 (depends on 10) The semiconductor device of claim 10, wherein the number of the plurality of second multi-bridge channels is greater than the number of the plurality of first multi-bridge channels. ### Claim 12 (depends on 10) The semiconductor device of claim 10, wherein the number of the plurality of second multi-bridge channels is greater than the number of the plurality of third multi-bridge channels. ### Claim 13 (depends on 10) The semiconductor device of claim 10, further comprising: a second inverter including a second load transistor and a second drive transistor; and a second transfer transistor connected to an output node of the second inverter. ### Claim 14 (depends on 13) The semiconductor device of claim 13, wherein the second load transistor includes a plurality of fourth multi-bridge channels, the second drive transistor includes a plurality of fifth multi-bridge channels, the second transfer transistor includes a plurality of sixth multi-bridge channels, and the number of the plurality of sixth multi-bridge channels is greater than the number of the plurality of fourth multi-bridge channels. ### Claim 15 (depends on 10) The semiconductor device of claim 10, wherein each of the plurality of first, second and third multi-bridge channels includes a plurality of nano-bridges that are stacked on a semiconductor substrate and spaced apart from one another, and each of the plurality of nano-bridges has a circular sectional shape, an elliptical circular sectional shape or a quadrangular sectional shape.