# US 10,374,096 B2 · Semiconductor device

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- Number: US 10,374,096 B2
- Document ID: US10374096B2
- Status: Granted
- Kind: B2
- Application number: 15/713,077
- Filed: 2017-09-22
- Published: 2018-01-11
- Granted: 2019-08-06
- Earliest claimed: 2014-06-25
- Assignees: Japan Display Inc.
- Applicants: Japan Display Inc.
- Inventors: Miyuki Ishikawa; Arichika Ishida; Masayoshi Fuchi; Hajime Watakabe; Takashi Okada
- Web page: https://patentgrep.com/patent/US10374096B2

## CPC

- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 30/6723: {having light shields}
- H10D 30/6729: {characterised by the electrodes}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 30/6758: {characterised by the insulating substrates}
- H10D 64/011: {of electrodes ohmically coupled to a semiconductor}
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/60: wherein the TFTs are in active matrices
- H10D 99/00: Subject matter not provided for in other groups of this subclass
- H10K 59/126: Shielding, e.g. light-blocking means over the TFTs
- H10P 50/20: Dry etching; Plasma etching; Reactive-ion etching
- H10P 50/69: {using masks for semiconductor materials}
- H10P 52/00: Grinding, lapping or polishing of wafers, substrates or parts of devices
- H10P 95/70: Chemical treatments
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

According to one embodiment, a semiconductor device includes contact holes passing through a source region of a drain region of an interlayer insulating film and oxide semiconductor layer to reach an insulating substrate, wherein a source electrode and a drain electrode are formed inside the contact holes, respectively.

## Claims

### Claim 1

A semiconductor device comprising:
a support substrate;
a metal layer formed on the support substrate;
an undercoat layer made of an insulating material and formed to cover the metal layer;
a semiconductor layer formed on the undercoat layer, the semiconductor layer including a channel region, and a source region and a drain region disposed at sides of the channel region;
a gate insulating film formed on the channel region;
a gate electrode formed on the gate insulating film;
an interlayer insulating film covering the gate electrode, the semiconductor layer, and the gate insulating film;
a source electrode electrically connected with the source region;
a drain electrode electrically connected with the drain region; and
an interconnection formed in the same layer and with the same material as the gate electrode, the interconnection provided between an insulating film formed in the same layer and with the same material as the gate insulating film and the interlayer insulating film;
wherein at least one of the source electrode and the drain electrode contacts the semiconductor layer and passes through one contact hole provided in the interlayer insulating film and the undercoat layer to electrically connect with the metal layer while passing through a different contact hole provided in the interlayer insulating film, but not through the undercoat layer, to electrically connect with the interconnection.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the metal layer comprises a first metal layer electrically connected with the source electrode and a second metal layer electrically connected with the drain electrode, and the first metal layer and the second metal layer are separated from each other.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein at least one of the source electrode and the drain electrode contacts a side face of the semiconductor layer to electrically connect with the metal layer.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein at least one of the source electrode and the drain electrode passes through the semiconductor layer to electrically connect with the metal layer.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the semiconductor layer is made of oxide semiconductor.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the semiconductor layer has a thickness of 30 to 40 nm.