# US 10,374,093 B2 · Method of fabricating a flexible substrate and the flexible substrate fabricated thereby

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- Number: US 10,374,093 B2
- Document ID: US10374093B2
- Status: Granted
- Kind: B2
- Application number: 15/812,231
- Filed: 2017-11-14
- Published: 2018-06-14
- Granted: 2019-08-06
- Earliest claimed: 2016-12-08
- Assignees: Electronics and Telecommunications Research Institute
- Applicants: Electronics and Telecommunications Research Institute
- Inventors: Doo-Hee Cho; Young Sam Park; Chunwon Byun; Byoung Gon Yu; Jonghee Lee; Hyunkoo Lee; Nam Sung Cho
- Web page: https://patentgrep.com/patent/US10374093B2

## CPC

- H10P 90/00: Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
- H10D 30/67: Thin-film transistors [TFT] {(Stacked nanowire, nanosheet or nanoribbon FETs H10D30/501)}
- H10D 30/6725: {having supplementary regions or layers for improving the flatness of the device}
- H10D 30/6758: {characterised by the insulating substrates}
- H10D 64/27: Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D 64/512: {Disposition of the gate electrodes, e.g. buried gates}
- H10D 86/0214: {using temporary substrates}
- H10D 86/0241: {using liquid deposition, e.g. printing}
- H10D 86/411: {characterised by materials, geometry or structure of the substrates}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/60: wherein the TFTs are in active matrices
- H10K 10/80: Constructional details
- H10K 71/13: using printing techniques, e.g. ink-jet printing or screen printing
- H10K 71/60: Forming conductive regions or layers, e.g. electrodes
- H10P 14/265: {using solutions}
- H10P 14/46: using a liquid
- H10P 14/6346: {using printing, e.g. ink-jet printing}
- H10P 72/70: for supporting or gripping
- H10P 72/74: {using temporarily an auxiliary support}
- H10D 30/0316: {of lateral bottom-gate TFTs comprising only a single gate}
- H10D 30/0321: {comprising silicon, e.g. amorphous silicon or polysilicon}
- H10D 30/6743: {Silicon}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 99/00: Subject matter not provided for in other groups of this subclass
- H10K 10/466: {Lateral bottom-gate IGFETs comprising only a single gate}
- H10K 85/623: {containing five rings, e.g. pentacene}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3426: {Oxides}
- H10P 14/3434: {being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424)}
- H10P 72/7412: {the auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support}
- H10P 72/7426: {used as a support during build up manufacturing of active devices}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES

## Abstract

Embodiments of the inventive concepts provide a method of fabricating a flexible substrate and the flexible substrate fabricated thereby. The method includes printing a gate catalyst pattern on a separation layer, forming a gate plating pattern on the gate catalyst pattern, forming a gate insulating layer on the gate plating pattern, printing a source catalyst pattern and a drain catalyst pattern spaced apart from each other on the gate insulating layer, and forming a source plating pattern and a drain plating pattern on the source catalyst pattern and the drain catalyst pattern, respectively.

## Claims

### Claim 1

A method of fabricating a flexible substrate, the method comprising:
forming a separation layer on a carrier substrate;
printing a gate catalyst pattern on the separation layer;
forming a gate plating pattern on the gate catalyst pattern;
forming a gate insulating layer on the gate plating pattern;
printing a source catalyst pattern and a drain catalyst pattern spaced apart from each other on the gate insulating layer;
forming a source plating pattern and a drain plating pattern on the source catalyst pattern and the drain catalyst pattern, respectively, such that the source plating pattern and the drain plating pattern are spaced apart from each other, exposing the gate insulating layer between the source plating pattern and the drain plating pattern;
forming an active pattern covering the source plating pattern, the drain plating pattern, and the gate insulating layer exposed between the source plating pattern and the drain plating pattern;
forming a first substrate layer that is flexible and covers an entire top surface of the carrier substrate on which the active pattern is formed; and
removing the separation layer and the carrier substrate.

### Claim 2 (depends on 1)

The method of claim 1, wherein the forming of the gate insulating layer comprises:
printing and thermally treating a precursor solution including a material of the gate insulating layer.

### Claim 3 (depends on 1)

The method of claim 1, further comprising:
forming a second substrate layer, which is flexible, on the separation layer before the printing of the gate catalyst pattern.

### Claim 4 (depends on 1)

The method of claim 1, further comprising:
forming a back-channel protecting layer covering the active pattern before the forming of the first substrate layer.

### Claim 5 (depends on 1)

The method of claim 1, further comprising:
forming a gas barrier layer covering an entire top surface of the carrier substrate having the active pattern before the forming of the first substrate layer.

### Claim 6 (depends on 1)

The method of claim 1, further comprising:
forming a protective film covering at least a portion of the first substrate layer after the removing of the separation layer and the carrier substrate.

### Claim 7 (depends on 1)

The method of claim 1, wherein the separation layer and the gate plating pattern are formed of different materials from each other.