# US 10,374,092 B2 · Power amplifier ramping and power control with forward and reverse back-gate bias

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- Number: US 10,374,092 B2
- Document ID: US10374092B2
- Status: Granted
- Kind: B2
- Application number: 15/488,615
- Filed: 2017-04-17
- Published: 2018-10-18
- Granted: 2019-08-06
- Earliest claimed: 2017-04-17
- Assignees: Globalfoundries Inc.
- Applicants: Globalfoundries Inc.
- Inventors: Arul Balasubramaniyan; Thomas Gregory Mckay
- Web page: https://patentgrep.com/patent/US10374092B2

## CPC

- H10D 30/6758: {characterised by the insulating substrates}
- H03F 1/0277: {Selecting one or more amplifiers from a plurality of amplifiers}
- H03F 1/223: {with MOSFET's}
- H03F 3/195: in integrated circuits
- H03F 3/245: {with semiconductor devices only}
- H03F 3/45179: {using MOSFET transistors as the active amplifying circuit (H03F3/45278 takes precedence)}
- H03F 3/72: Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
- H10D 30/6734: {having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs}
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H03F 2200/451: the amplifier being a radio frequency amplifier
- H03F 2200/511: Many discrete supply voltages or currents or voltage levels can be chosen by a control signal in an IC-block amplifier circuit
- H03F 2203/45112: the biasing of the differential amplifier being controlled from the input or the output signal
- H03F 2203/45228: A transformer being added at the output or the load circuit of the dif amp
- H03F 2203/45342: the AAC comprising control means on a back gate of the AAC
- H03F 2203/45394: the AAC of the dif amp comprising FETs whose sources are not coupled, i.e. the AAC being a pseudo-differential amplifier
- H03F 2203/45731: the LC comprising a transformer
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H03F: AMPLIFIERS

## Abstract

Embodiments of the present disclosure provide a circuit structure and method for power amplifier control with forward and reverse voltage biases to transistor back-gate regions. A circuit structure according to the disclosure can include: a power amplifier (PA) circuit having first and second transistors, the first and second transistors each including a back-gate region, wherein the back-gate region of each of the first and second transistors is positioned within a doped substrate separated from a semiconductor region by a buried insulator layer; and an analog voltage source coupled to the back-gate regions of the first and second transistors of the PA circuit, such that the analog voltage source alternatively supplies a forward bias voltage or a reverse bias voltage to the back-gate regions of the first and second transistors of the PA circuit to produce a continuously sloped power ramping profile.

## Claims

### Claim 1

A circuit structure comprising:
a power amplifier (PA) circuit having first and second transistors, the first and second transistors each including a back-gate region, wherein the back-gate region of each of the first and second transistors is positioned within a doped substrate separated from a semiconductor region by a buried insulator layer; and
an analog voltage source coupled to the back-gate regions of the first and second transistors of the PA circuit, such that the analog voltage source alternatively supplies a forward bias voltage or a reverse bias voltage to the back-gate regions of the first and second transistors of the PA circuit to produce a continuously sloped power ramping profile.

### Claim 2 (depends on 1)

The circuit structure of claim 1, wherein the shared substrate comprises a fully-depleted semiconductor-on-insulator (FDSOI) substrate.

### Claim 3 (depends on 1)

The circuit structure of claim 1, wherein the analog voltage source is further configured to switch between the positive bias voltage and the negative bias voltage during operation of the PA circuit in an active mode.

### Claim 4 (depends on 1)

The circuit structure of claim 1, wherein the first and second transistors comprise portions of a cascode PA circuit.

### Claim 5 (depends on 4)

The circuit structure of claim 4, wherein the cascode PA circuit further includes:
a third transistor having a source/drain region electrically coupled to a source/drain region of the first transistor; and
a fourth transistor having a source/drain region electrically coupled to a source/drain region of the second transistor,
the third and fourth transistor each including a back-gate region, and wherein the analog voltage source is electrically coupled to the back-gate regions of the third and fourth transistors of the cascode PA circuit, such that the analog voltage source alternatively supplies a forward bias voltage or a reverse bias voltage to the back-gate regions of the third and fourth transistors of the cascode PA circuit.

### Claim 6 (depends on 1)

The circuit structure of claim 1, wherein the PA circuit comprises part of a digital power amplifier (DPA) cell in an array of DPA cells.

### Claim 7 (depends on 1)

The circuit structure of claim 1, wherein an input voltage to the PA circuit is independent from an output voltage of the PA circuit.

### Claim 8 (depends on 1)

The circuit structure of claim 1, wherein the analog voltage source supplies the forward bias voltage or the reverse bias voltage based on an operating mode and a temperature of the circuit structure.

### Claim 9

A method for adjusting power amplification in a circuit structure, the method comprising:
applying one of a forward or a reverse voltage bias to first and second transistors in a power amplifier (PA) circuit at back-gate regions thereof during operation in a dormant mode, the back-gate regions of the first and second transistors including a doped substrate separated from a channel region by a buried insulator layer;
operating the circuit structure in an active mode; and
applying the other of the forward or the reverse voltage bias to the back-gate regions of the first and second transistors in the power amplifier (PA) circuit while operating the circuit structure in the active mode to produce a continuously sloped power ramping profile.

### Claim 10 (depends on 9)

The method of claim 9, wherein a ramping time between the dormant mode and the active mode is at most approximately three microseconds (μs) during the applying of the other of the forward or the reverse voltage bias to the back-gate regions of the first and second transistors in the PA circuit, and wherein a voltage profile of the PA circuit is continuously sloped during the ramping time.

### Claim 11 (depends on 9)

The method of claim 9, wherein operating the circuit structure in the active mode while applying the other of the forward or the reverse voltage bias yields a continuously sloped power output from the PA circuit between operation in the dormant mode and operation in the active mode.

### Claim 12 (depends on 9)

The method of claim 9, wherein the back-gate terminals of the first and second transistors are positioned within a fully-depleted semiconductor-on-insulator (FDSOI) substrate.

### Claim 13 (depends on 9)

The method of claim 9, wherein applying the other of the forward or the reverse voltage bias to the back-gate terminals of the first and second transistors in the PA circuit includes signaling an analog voltage source to produce the other of the forward or the reverse voltage bias.

### Claim 14 (depends on 13)

The method of claim 13, further comprising adjusting a power output from a digital lookup table (LUT) of the analog voltage before applying the other of the forward or the reverse voltage bias to the back-gate terminals of the first and second transistors in the PA circuit.

### Claim 15 (depends on 9)

The method of claim 9, further comprising applying the other of the forward or the reverse voltage bias to the back-gate terminals of the first and second transistors in the PA circuit while operating the circuit structure an elevated temperature.

### Claim 16

A circuit structure comprising:
a power amplifier (PA) circuit having first and second transistors, each of the first and second transistors including:
a dopant-implanted substrate, the dopant-implanted substrate defining a back-gate region;
a buried insulator layer positioned on the dopant-implanted substrate, and
a fully-depleted semiconductor-on-insulator (FDSOI) layer positioned on the buried insulator layer, wherein the buried insulator layer separates the FDSOI layer from the back-gate region, wherein the FDSOI layer includes a source region, a channel region, and a drain region; and
an analog voltage source electrically coupled to the back-gate regions of the first and second transistors of the PA circuit, such that the analog voltage source alternatively supplies a forward bias voltage or a reverse bias voltage to the back-gate regions of the first and second transistors of the PA circuit to produce a continuously sloped power ramping profile.

### Claim 17 (depends on 16)

The circuit structure of claim 16, wherein the analog voltage source is further configured to switch between the forward bias voltage and the reverse bias voltage during operation of the PA circuit in an active mode.

### Claim 18 (depends on 16)

The circuit structure of claim 16, wherein the analog voltage source includes:
a digital lookup table (LUT) having an input node coupled to a device;
a digital-analog-converter (DAC) having an input node coupled to an output from the LUT; and
a filter circuit having an input node coupled to an output from the DAC, and an output node coupled to the back-gate regions of the first and second transistors of the PA circuit.

### Claim 19 (depends on 16)

The circuit structure of claim 16, wherein an input voltage to the PA circuit is independent from an output voltage of the PA circuit.

### Claim 20 (depends on 16)

The circuit structure of claim 16, wherein the analog voltage source supplies the forward bias voltage or the reverse bias voltage based on an operating mode and a temperature of the circuit structure.