# US 10,374,089 B2 · Tensile strain in NFET channel

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- Number: US 10,374,089 B2
- Document ID: US10374089B2
- Status: Granted
- Kind: B2
- Application number: 15/852,109
- Filed: 2017-12-22
- Published: 2019-06-27
- Granted: 2019-08-06
- Earliest claimed: 2017-12-22
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Peng Xu; Kangguo Cheng; Juntao Li; Heng Wu
- Web page: https://patentgrep.com/patent/US10374089B2

## CPC

- H10D 30/798: {being provided in or under the channel regions}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/235: {of IGFETs (IGFETs having buried channels H10D30/637)}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/6308: {of Group IV semiconductors}
- H10P 14/6927: {the material being a silicon oxynitride, e.g. SiON or SiON:H}
- H10P 14/69433: {the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz}
- H10P 50/283: {by chemical means}
- H10P 95/062: {involving a dielectric removal step}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method of forming a semiconductor structure includes forming a fin in a film stack disposed over a top surface of a substrate, the film stack comprising a first semiconductor layer, a second semiconductor layer and a channel layer. The method also includes forming an oxide layer disposed over the top surface of the substrate surrounding the fin, the oxide layer covering sidewalls of the first semiconductor layer and the second semiconductor layer, performing a channel release to remove the second semiconductor layer, and performing an oxidation to form a non-uniform thickness of an additional oxide layer along a length of the fin, the non-uniform thickness providing a vertical compressive strain that induces lateral tensile strain in the channel layer. The channel layer comprises an n-type field-effect transistor (NFET) channel.

## Claims

### Claim 1

A method of forming a semiconductor structure, comprising:
forming a fin in a film stack disposed over a top surface of a substrate, the film stack comprising a first semiconductor layer, a second semiconductor layer and a channel layer;
forming an oxide layer disposed over the top surface of the substrate surrounding the fin, the oxide layer covering sidewalls of the first semiconductor layer and the second semiconductor layer;
performing a channel release to remove the second semiconductor layer; and
performing an oxidation to form a non-uniform thickness of an additional oxide layer along a length of the fin, the non-uniform thickness providing a vertical compressive strain that induces lateral tensile strain in the channel layer;
wherein the channel layer comprises an n-type field-effect transistor (NFET) channel; and
wherein the first semiconductor layer comprises silicon germanium (SiGe) with a first percentage of germanium (Ge), the second semiconductor layer comprises SiGe with a second percentage of Ge higher than the first percentage, and the channel layer comprises silicon (Si).

### Claim 2 (depends on 1)

The method of claim 1, wherein the oxidation comprises a low-temperature oxidation.

### Claim 3

A method of forming a semiconductor structure, comprising:
forming a fin in a film stack disposed over a top surface of a substrate, the film stack comprising a first semiconductor layer, a second semiconductor layer and a channel layer;
forming an oxide layer disposed over the top surface of the substrate surrounding the fin, the oxide layer covering sidewalls of the first semiconductor layer and the second semiconductor layer;
performing a channel release to remove the second semiconductor layer; and
performing an oxidation to form a non-uniform thickness of an additional oxide layer along a length of the fin, the non-uniform thickness providing a vertical compressive strain that induces lateral tensile strain in the channel layer;
wherein the channel layer comprises an n-type field-effect transistor (NFET) channel; and
wherein the non-uniform thickness of the additional oxide layer along the length of the fin comprises an inner portion of the oxide layer disposed below a center of the channel layer of the fin having a smaller thickness than outer portions of the additional oxide layer proximate ends of the fin.

### Claim 4

A method of forming a semiconductor structure, comprising:
forming a fin in a film stack disposed over a top surface of a substrate, the film stack comprising a first semiconductor layer, a second semiconductor layer and a channel layer;
forming an oxide layer disposed over the top surface of the substrate surrounding the fin, the oxide layer covering sidewalls of the first semiconductor layer and the second semiconductor layer;
performing a channel release to remove the second semiconductor layer; and
performing an oxidation to form a non-uniform thickness of an additional oxide layer along a length of the fin, the non-uniform thickness providing a vertical compressive strain that induces lateral tensile strain in the channel layer;
wherein the channel layer comprises an n-type field-effect transistor (NFET) channel; and
wherein forming the oxide layer comprises:
forming an oxide disposed over the top surface of the substrate surrounding the at least one fin;
forming a dummy gate disposed over a top surface of a portion of the channel layer and over portions of the oxide surrounding the portion of the channel layer;
forming a capping layer over a top surface of the dummy gate; and
forming a spacer on sidewalls of the dummy gate and the capping layer.

### Claim 5 (depends on 4)

The method of claim 4, wherein the dummy gate comprises amorphous silicon (a-Si), the capping layer comprises silicon nitride (SiN), and the spacer comprises silicon boron carbide nitride (SiBCN).

### Claim 6 (depends on 4)

The method of claim 4, further comprising:
recessing the channel layer and a portion of the second semiconductor layer exposed by the spacer; and
performing the channel release to remove remaining portions of the second semiconductor layer.

### Claim 7 (depends on 6)

The method of claim 6, further comprising:
forming a liner on exposed surfaces of the channel layer, the first semiconductor layer, and the spacer; and
forming a nitride layer:
disposed between (i) the bottom surface of the liner disposed on a bottom surface of the channel layer and (ii) a top surface of the liner disposed on a top surface of the first semiconductor layer; and
on sidewalls of the liner disposed on sidewalls of the spacer.

### Claim 8 (depends on 7)

The method of claim 7, wherein the liner comprises silicon oxynitride (SiON) and the nitride layer comprises silicon nitride (SiN).

### Claim 9 (depends on 7)

The method of claim 7, further comprising etching portions of the liner and the nitride layer to expose sidewalls of the channel layer.

### Claim 10 (depends on 9)

The method of claim 9, further comprising:
forming source/drain regions over a top surface of the oxide layer adjacent exposed sidewalls of the channel layer; and
forming another additional oxide layer disposed over top surfaces of the source/drain regions.

### Claim 11 (depends on 10)

The method of claim 10, wherein forming the other additional oxide layer comprises filling with an oxide and planarizing a top surface of the oxide with a top surface of the capping layer using chemical mechanical polishing (CMP).

### Claim 12 (depends on 10)

The method of claim 10, further comprising:
removing the dummy gate and the capping layer;
forming a gate dielectric on a top surface of the channel layer and on a portion of exposed sidewalls of the spacers;
forming a gate conductor disposed over the gate dielectric; and
forming a self-aligned contact (SAC) capping layer disposed over top surfaces of the gate dielectric and the gate conductor between exposed sidewalls of the spacer.

### Claim 13 (depends on 1)

The method of claim 1, wherein the gate dielectric comprises a high-k dielectric material, the gate conductor comprises a metal, and the SAC capping layer comprises silicon nitride (SiN).

### Claim 14 (depends on 1)

The method of claim 1, wherein the non-uniform thickness of the additional oxide layer along the length of the fin comprises an inner portion of the oxide layer disposed below a center of the channel layer of the fin having a smaller thickness than outer portions of the additional oxide layer proximate ends of the fin.

### Claim 15 (depends on 1)

The method of claim 1, wherein forming the oxide layer comprises:
forming an oxide disposed over the top surface of the substrate surrounding the at least one fin;
forming a dummy gate disposed over a top surface of a portion of the channel layer and over portions of the oxide surrounding the portion of the channel layer;
forming a capping layer over a top surface of the dummy gate; and
forming a spacer on sidewalls of the dummy gate and the capping layer.

### Claim 16 (depends on 3)

The method of claim 3, wherein the first semiconductor layer comprises silicon germanium (SiGe) with a first percentage of germanium (Ge), the second semiconductor layer comprises SiGe with a second percentage of Ge higher than the first percentage, and the channel layer comprises silicon (Si).

### Claim 17 (depends on 3)

The method of claim 3, wherein forming the oxide layer comprises:
forming an oxide disposed over the top surface of the substrate surrounding the at least one fin;
forming a dummy gate disposed over a top surface of a portion of the channel layer and over portions of the oxide surrounding the portion of the channel layer;
forming a capping layer over a top surface of the dummy gate; and
forming a spacer on sidewalls of the dummy gate and the capping layer.

### Claim 18 (depends on 4)

The method of claim 4, wherein the first semiconductor layer comprises silicon germanium (SiGe) with a first percentage of germanium (Ge), the second semiconductor layer comprises SiGe with a second percentage of Ge higher than the first percentage, and the channel layer comprises silicon (Si).