# US 10,374,087 B2 · Semiconductor devices and methods of manufacturing the same

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- Number: US 10,374,087 B2
- Document ID: US10374087B2
- Status: Granted
- Kind: B2
- Application number: 14/956,908
- Filed: 2015-12-02
- Published: 2016-06-09
- Granted: 2019-08-06
- Earliest claimed: 2014-12-04
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Dae-Won Kim; Jae-Kyu Lee
- Web page: https://patentgrep.com/patent/US10374087B2

## CPC

- H10D 30/792: {comprising applied insulating layers, e.g. stress liners}
- H10B 61/22: {of the field-effect transistor [FET] type}
- H10D 30/0297: {using recessing of the gate electrodes, e.g. to form trench gate electrodes}
- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/0143: {comprising concurrently refilling multiple trenches having different shapes or dimensions}
- H10W 10/0145: {of trenches having shapes other than rectangular or V-shape (H10W10/0143 takes precedence)}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a substrate, first and second isolation layers, an insulation layer pattern, and a gate structure. The substrate has a cell region and a peripheral region. The first isolation layer is buried in a first upper portion of the substrate in the peripheral region. The second isolation layer is buried in a second upper portion of the substrate in the cell region, and extends along a first direction substantially parallel to a top surface of the substrate. The insulation layer pattern is buried in the first upper portion, and extends along a second direction substantially parallel to the top surface of the substrate and substantially perpendicular to the first direction. The insulation layer pattern has a lower surface higher than a lower surface of the second isolation layer, and applies a stress to a portion of the substrate adjacent thereto.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate having a cell region and a peripheral region;
a first isolation layer buried in a first upper portion of the substrate, the first upper portion being in the peripheral region;
a second isolation layer buried in a second upper portion of the substrate, the second upper portion being in the cell region, and the second isolation layer extending along a first direction substantially parallel to a top surface of the substrate;
an insulation layer pattern buried in the second upper portion, the insulation layer pattern extending along a second direction, and the second direction being substantially parallel to the top surface of the substrate and substantially perpendicular to the first direction,
the insulation layer pattern having a lower surface higher than a lower surface of the second isolation layer, and
the insulation layer pattern applying a stress to a portion of the substrate adjacent thereto; and
a gate structure on the substrate in the cell region;
wherein the gate structure extends along the second direction in the second upper portion, and
the gate structure includes,
a gate insulation layer on a bottom and a sidewall of a gate trench;
a gate electrode on the gate insulation layer, the gate electrode filling a lower portion of the gate trench; and
a gate mask on the gate electrode, the gate mask filling an upper portion of the gate trench; and
wherein a width of a bottom portion of the insulation layer pattern is greater than a width of a top portion of the insulation layer pattern, and the width of the top portion of the insulation layer pattern is less than a width of a top of the gate trench.

### Claim 2

A semiconductor device, comprising:
a substrate having a cell region and a peripheral region;
a first isolation layer buried in a first upper portion of the substrate, the first upper portion being in the peripheral region;
a second isolation layer buried in a second upper portion of the substrate, the second upper portion being in the cell region, and the second isolation layer extending along a first direction substantially parallel to a top surface of the substrate;
an insulation layer pattern buried in the second upper portion, the insulation layer pattern extending along a second direction, and the second direction being substantially parallel to the top surface of the substrate and substantially perpendicular to the first direction,
the insulation layer pattern having a lower surface higher than a lower surface of the second isolation layer, and
the insulation layer pattern applying a stress to a portion of the substrate adjacent thereto; and
a gate structure on the substrate in the cell region;
wherein a width of a bottom portion of the insulation layer pattern is greater than a width of a top portion of the insulation layer pattern.