# US 10,374,086 B2 · 3D transistor having a gate stack including a ferroelectric film

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- Number: US 10,374,086 B2
- Document ID: US10374086B2
- Status: Granted
- Kind: B2
- Application number: 15/369,809
- Filed: 2016-12-05
- Published: 2017-06-08
- Granted: 2019-08-06
- Earliest claimed: 2015-12-04
- Assignees: The Regents of the University of California
- Applicants: The Regents of the University of California
- Inventors: Chenming Hu
- Web page: https://patentgrep.com/patent/US10374086B2

## CPC

- H10D 30/701: {IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs}
- H10D 30/0415: {of FETs having ferroelectric gate insulators}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/47: having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/673: {characterised by the shapes, relative sizes or dispositions of the gate electrodes}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6739: {Conductor-insulator-semiconductor electrodes}
- H10D 30/674: {characterised by the active materials}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/689: {having ferroelectric layers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A three-dimensional (3D) transistor includes a ferroelectric film between the gate and the channel. The 3D transistor can be characterized as a 3D Negative Capacitance (NC) transistor due to the negative capacitance resulting from the ferroelectric film. Performance of the transistor is optimized by manipulating the structure and/or by the selection of materials. In one example, the capacitance of the ferroelectric film (CFE) is matched to the sum of the gate capacitance (CMOS) and the gate edge capacitance (CEDGE), wherein the gate edge capacitance (CEDGE) is the capacitance at the edge of the gate and between the gate and the source and its extension, and the gate and the drain and its extension.

## Claims

### Claim 1

A 3D transistor comprising:
a drain;
a source;
a channel longitudinally extending between the drain and the source;
a gate positioned over at least two lateral sides of the channel and having a gate length less than 22 nm; and
a ferroelectric film between the gate and the channel for at least a portion of the region between the gate and the channel, the 3D transistor having a structure configured to operate with less than 59 mV per decade subthreshold swing at room temperature, the ferroelectric film having a ferroelectric capacitance substantially matched, over an operating range of a gate voltage, to a sum of a gate to channel capacitance (CMOS) and a gate edge capacitance (CEDGE), the CEDGE resulting between at the edge portion of the gate and between the gate and the source and the source extension, and the gate and the drain and the drain extension.

### Claim 2 (depends on 1)

The 3D transistor of claim 1, wherein the 3D transistor has a structure selected from the group comprising FinFET, nanowire FET, Gate-All-Around FET, nanowire FinFET, Omega FET, and nanotube FET structures and combinations thereof.

### Claim 3 (depends on 1)

The 3D transistor of claim 1, wherein a ferroelectric capacitance of the ferroelectric film is substantially matched to a gate to channel capacitance (CMOS) over an operating range of a gate voltage.

### Claim 4 (depends on 1)

The 3D transistor of claim 1, wherein the ferroelectric film has a thickness less than 10.0 nm.

### Claim 5 (depends on 4)

The 3D transistor of claim 4, wherein the ferroelectric film has a thickness less than 7.0 nm.

### Claim 6 (depends on 1)

The 3D transistor of claim 1, wherein the ferroelectric film comprises a film selected from the group comprising: hafnium zirconium oxide, hafnium oxide, zirconium oxide, Pb(Zr,Ti)O, and BaTiO.

### Claim 7 (depends on 1)

The 3D transistor of claim 1, further comprising an internal conductive gate positioned between the channel and the ferroelectric film.

### Claim 8 (depends on 7)

The 3D transistor of claim 7, wherein a material of the internal gate is selected from the group comprising TiN, TaN, Ru, W, and Si.

### Claim 9 (depends on 7)

The 3D transistor of claim 7, wherein the gate is in close proximity to only a portion of the internal gate and configured to reduce the effective area of the gate to internal gate ferroelectric capacitor area.

### Claim 10 (depends on 1)

The 3D transistor of claim 1, further comprising a dielectric film between the channel and the ferroelectric film.

### Claim 11 (depends on 10)

The 3D transistor of claim 10, wherein the dielectric film is selected from the group consisting of SiO2 and SiON and wherein the gate is a metal gate.

### Claim 12 (depends on 10)

The 3D transistor of claim 10, further comprising a gate dielectric with an effective oxide thickness (EOT) more than 0.8 nm.

### Claim 13 (depends on 1)

The 3D transistor of claim 1, wherein the structure is configured to have a current-voltage characteristic similar to a MOSFET without a ferroelectric film, the current-voltage characteristic not having significant hysteresis.

### Claim 14

A method of fabricating a three-dimensional transistor configured to operate with less than 59 mV per decade subthreshold swing at room temperature, the method comprising:
forming a drain;
forming a source;
forming a channel longitudinally extending between the drain and the source;
forming a gate positioned over at least two lateral sides of the channel and having a gate length less than 22 nm; and
forming a ferroelectric film between the gate and the channel for at least a portion of the region between the gate and the channel; and
substantially matching, over an operating range of a gate voltage, a ferroelectric capacitance of the ferroelectric film to a sum of a gate to channel capacitance (CMOS) and a gate edge capacitance (CEDGE), the CEDGE resulting at the edge of the gate and between the gate and the source and its extension, and the gate and the drain and its extension.

### Claim 15 (depends on 14)

The method of claim 14, wherein the forming the ferroelectric film comprises forming the ferroelectric film to have an effective oxide thickness (EOT) greater than 0.8 nm.

### Claim 16 (depends on 14)

The method of claim 14, further comprising forming a gate dielectric between the channel and the ferroelectric film, wherein the gate dielectric and the ferroelectric film are formed in the same deposition tool without breaking vacuum.

### Claim 17

A 3D transistor comprising:
a drain;
a source;
a channel longitudinally extending between the drain and the source;
a gate positioned over at least two lateral sides of the channel and having a gate length less than 22 nm; and
a ferroelectric film between the gate and the channel for at least a portion of the region between the gate and the channel, the 3D transistor having a structure configured to operate with less than 59 mV per decade subthreshold swing at room temperature, the ferroelectric film having a ferroelectric capacitance substantially matched to a gate to channel capacitance (CMOS) over an operating range of a gate voltage.

### Claim 18 (depends on 17)

The 3D transistor of claim 17, wherein the 3D transistor has a structure selected from the group comprising FinFET, nanowire FET, Gate-All-Around FET, nanowire FinFET, Omega FET, and nanotube FET structures and combinations thereof.

### Claim 19 (depends on 17)

The 3D transistor of claim 17, wherein a ferroelectric capacitance of the ferroelectric film is substantially matched, over an operating range of a gate voltage, to a sum of a gate to channel capacitance (CMOS) and a gate edge capacitance (CEDGE), the CEDGE resulting between at the edge portion of the gate and between the gate and the source and the source extension, and the gate and the drain and the drain extension.

### Claim 20 (depends on 17)

The 3D transistor of claim 17, wherein the ferroelectric film has a thickness less than 10.0 nm.

### Claim 21 (depends on 20)

The 3D transistor of claim 20, wherein the ferroelectric film has a thickness less than 7.0 nm.

### Claim 22 (depends on 17)

The 3D transistor of claim 17, wherein the ferroelectric film comprises a film selected from the group comprising: hafnium zirconium oxide, hafnium oxide, zirconium oxide, Pb(Zr,Ti)O, and BaTiO.

### Claim 23 (depends on 17)

The 3D transistor of claim 17, further comprising an internal conductive gate positioned between the channel and the ferroelectric film.

### Claim 24 (depends on 17)

The 3D transistor of claim 17, further comprising a dielectric film between the channel and the ferroelectric film.

### Claim 25 (depends on 24)

The 3D transistor of claim 24, wherein the dielectric film is selected from the group consisting of SiO2 and SiON and wherein the gate is a metal gate.

### Claim 26 (depends on 24)

The 3D transistor of claim 24, further comprising a gate dielectric with an effective oxide thickness (EOT) more than 0.8 nm.

### Claim 27

A 3D transistor comprising:
a drain;
a source;
a channel longitudinally extending between the drain and the source;
a gate positioned over at least two lateral sides of the channel and having a gate length less than 22 nm;
a ferroelectric film between the gate and the channel for at least a portion of the region between the gate and the channel;
an internal conductive gate positioned between the channel and the ferroelectric film, the gate in close proximity to only a portion of the internal gate and configured to reduce the effective area of the gate to internal gate ferroelectric capacitor area, the 3D transistor having a structure configured to operate with less than 59 mV per decade subthreshold swing at room temperature.

### Claim 28 (depends on 27)

The 3D transistor of claim 27, wherein the 3D transistor has a structure selected from the group comprising FinFET, nanowire FET, Gate-All-Around FET, nanowire FinFET, Omega FET, and nanotube FET structures and combinations thereof.

### Claim 29 (depends on 27)

The 3D transistor of claim 27, wherein a material of the internal gate is selected from the group comprising TiN, TaN, Ru, W, and Si.