# US 10,374,085 B2 · Semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,374,085 B2 - Document ID: US10374085B2 - Status: Granted - Kind: B2 - Application number: 15/997,793 - Filed: 2018-06-05 - Published: 2019-05-16 - Granted: 2019-08-06 - Earliest claimed: 2017-11-15 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Sang Young Kim; Deok Han Bae; Byung Chan Ryu; Da Un Jeon - Web page: https://patentgrep.com/patent/US10374085B2 ## CPC - H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]} - H10W 20/035: {combinations of barrier, adhesion or liner layers, e.g. multi-layered barrier layers} - H10W 20/082: {the openings being tapered via holes} - H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning} - H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes - H10W 20/42: Vias, e.g. via plugs - H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence) - H10D 64/668: {the layer being a silicide, e.g. TiSi2} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor device includes a first active region that extends on a substrate in a first direction, a second active region that extends in parallel with the first active region, an element isolation region between the first and second active regions, a gate structure that extends in a second direction different from the first direction, and intersects the first and second active regions, a lower contact spaced apart from the gate structure in the first direction, the lower contact being on the first active region, the element isolation region, and the second active region, and an upper contact on the lower contact between the first active region and the second active region. A width of the lower contact in the first direction that is on the first active region m narrower than a width of the lower contact in the first direction that is on the element isolation region. ## Claims ### Claim 1 A semiconductor device, comprising: a first active region that extends on a substrate in a first direction; a second active region that extends on the substrate in the first direction and in parallel with the first active region; an element isolation region between the first active region and the second active region; a gate structure that extends in a second direction different from the first direction, and intersects the first and second active regions; a lower contact spaced apart from the gate structure in the first direction, the lower contact being on the first active region, the element isolation region, and the second active region; and an upper contact on the lower contact between the first active region and the second active region, wherein a width of the lower contact in the first direction that is on the first active region is narrower than a width of the lower contact in the first direction that is on the element isolation region. ### Claim 2 (depends on 1) The semiconductor device as claimed in claim 1, wherein a width of a lower surface of the upper contact in the first direction is narrower than the width of the lower contact in the first direction that is on the element isolation region. ### Claim 3 (depends on 2) The semiconductor device as claimed in claim 2, wherein a width of an upper surface of the upper contact in the first direction is narrower than the width of the lower contact in the first direction that is on the element isolation region. ### Claim 4 (depends on 1) The semiconductor device as claimed in claim 1, wherein a width of a lower surface of the upper contact in the second direction is narrower than a width of the lower contact in the second direction that is on the element isolation region. ### Claim 5 (depends on 4) The semiconductor device as claimed in claim 4, wherein a width of an upper surface of the upper contact in the second direction is narrower than the width of the lower contact in the second direction that is on the element isolation region. ### Claim 6 (depends on 1) The semiconductor device as claimed in claim 1, wherein a width of the lower contact in the first direction that is on the second active region is narrower than the width of the lower contact in the first direction that is on the element isolation region. ### Claim 7 (depends on 1) The semiconductor device as claimed in claim 1, wherein a first distance between the gate structure and the lower contact on the first active region is greater than a second distance between the gate structure and the lower contact on the element isolation region. ### Claim 8 (depends on 7) The semiconductor device as claimed in claim 7, wherein a third distance between the gate structure and the lower contact on the second active region is greater than the second distance between the gate structure and the lower contact on the element isolation region. ### Claim 9 (depends on 1) The semiconductor device as claimed in claim 1, wherein the lower contact on the element isolation region is convexly formed so as to protrude toward a direction in which the gate structure is positioned. ### Claim 10 (depends on 1) The semiconductor device as claimed in claim 1, wherein a plane of the lower contact formed in parallel with a plane on which the substrate is arranged has an oval shape. ### Claim 11 A semiconductor device, comprising: a first active region that extends on a substrate in a first direction; a second active region that extends on the substrate in the first direction and in parallel with the first active region; an element isolation region between the first active region and the second active region; a first gate structure that extends in a second direction different from the first direction, and intersects the first and second active regions; a second gate structure that extends in the second direction and intersects the first and second active regions, the second gate structure being spaced apart from the first gate structure in the first direction; a lower contact that includes, between the first gate structure and the second gate structure, a first portion arranged on the first active region, a second portion arranged on the element isolation region, and a third portion arranged on the second active region; and an upper contact on the second portion of the lower contact, the upper contact having a width in the first direction that is narrower than a width of the second portion of the lower contact in the first direction, wherein a width of the first portion of the lower contact in the first direction is narrower than the width of the second portion of the lower contact in the first direction. ### Claim 12 (depends on 11) The semiconductor device as claimed in claim 11, wherein a width of the third portion of the lower contact in the first direction is narrower than the width of the second portion of the lower contact in the first direction. ### Claim 13 (depends on 11) The semiconductor device as claimed in claim 11, wherein a first distance between the first gate structure and the first portion of the lower contact is greater than a second distance between the first gate structure and the second portion of the lower contact. ### Claim 14 (depends on 11) The semiconductor device as claimed in claim 11, wherein a first distance between the first gate structure and the first portion of the lower contact is the same as a fourth distance between the second gate structure and the first portion of the lower contact. ### Claim 15 (depends on 11) The semiconductor device as claimed in claim 11, wherein a second distance between the first gate structure and the second portion of the lower contact is the same as a fifth distance between the second gate structure and the second portion of the lower contact. ### Claim 16 (depends on 11) The semiconductor device as claimed in claim 11, wherein the upper contact is spaced apart from the first and second active regions, respectively, in the second direction. ### Claim 17 A semiconductor device, comprising: first to fourth active regions that extend on a substrate in a first direction, respectively, and are spaced apart from one another in sequence in a second direction different from the first direction; a gate structure that extends in the second direction and intersects the first to fourth active regions; a first element isolation region between the first active region and the second active region; a second element isolation region between the second active region and the third active region; a third element isolation region between the third active region and the fourth active region; a lower contact spaced apart from the gate structure in the first direction, the lower contact being on the first to fourth active regions and the first to third element isolation regions; a first upper contact on the lower contact that overlaps the first element isolation region; a second upper contact on the lower contact that overlaps the second element isolation region; and a third upper contact on the lower contact that overlaps the third element isolation region, wherein a width of the lower contact in the first direction that overlaps each of the first to fourth active regions is narrower than a width of the lower contact in the first direction that overlaps each of the first to third element isolation regions. ### Claim 18 (depends on 17) The semiconductor device as claimed in claim 17, wherein a first distance between the gate structure and the lower contact on the first to fourth active regions is greater than a second distance between the gate structure and the lower contact on the first to third element isolation regions. ### Claim 19 (depends on 17) The semiconductor device as claimed in claim 17, wherein a width of each of the first to third upper contacts in the first direction is narrower than a width of the lower contact in the first direction that is on each of the first to third element isolation regions. ### Claim 20 (depends on 17) The semiconductor device as claimed in claim 17, wherein the lower contact arranged on the first to third element isolation region is convexly formed so as to protrude toward a direction in which the gate structure is positioned.