# US 10,374,083 B1 · Vertical fin field effect transistor with reduced gate length variations

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- Number: US 10,374,083 B1
- Document ID: US10374083B1
- Status: Granted
- Kind: B1
- Application number: 15/873,564
- Filed: 2018-01-17
- Published: 2019-07-18
- Granted: 2019-08-06
- Earliest claimed: 2018-01-17
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Chen Zhang; Kangguo Cheng; Xin Miao; Wenyu Xu
- Web page: https://patentgrep.com/patent/US10374083B1

## CPC

- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/292: {Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512)}
- H10D 62/364: {of IGFETs}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D 84/016: {the components including vertical IGFETs}
- H10D 84/0195: {the components including vertical IGFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 84/837: {comprising vertical IGFETs}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10P 50/242: {of Group IV materials}
- H10P 50/73: {using masks for insulating materials}
- H10W 10/011: {of isolation regions comprising dielectric materials}
- H10W 10/0145: {of trenches having shapes other than rectangular or V-shape (H10W10/0143 takes precedence)}
- H10W 10/10: Isolation regions comprising dielectric materials
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method of forming a fin field effect transistor is provided. The method includes forming an elevated substrate tier on a substrate, and forming a fin mesa on the elevated substrate tier with a fin template layer on the fin mesa, wherein the elevated substrate tier is laterally larger than the fin mesa and fin template layer. The method includes forming a fill layer on the substrate, wherein the fill layer surrounds the fin mesa, elevated substrate tier, and fin template layer, forming a plurality of fin masks on the fill layer and fin template layer, and removing portions of the fill layer, fin template layer, and fin mesa to form a plurality of dummy fins from the fill layer, one or more vertical fins from the fin mesa, and a dummy fin portion on opposite ends of each of the one or more vertical fins from the fill layer.

## Claims

### Claim 1

A method of forming a fin field effect transistor, comprising:
forming an elevated substrate tier on a substrate;
forming a fin mesa on the elevated substrate tier with a fin template layer on the fin mesa, wherein the elevated substrate tier is laterally larger than the fin mesa and fin template layer;
forming a fill layer on the substrate, wherein the fill layer surrounds the fin mesa, elevated substrate tier, and fin template layer;
forming a plurality of fin masks on the fill layer and fin template layer; and
removing portions of the fill layer, fin template layer, and fin mesa to form a plurality of dummy fins from the fill layer, one or more vertical fins from the fin mesa, and a dummy fin portion on opposite ends of each of the one or more vertical fins from the fill layer.

### Claim 2 (depends on 1)

The method of claim 1, wherein the material of the fill layer is selected from the group consisting of silicon oxide (SiO), silicon nitride (SiN), a silicon oxynitride (SiON), a silicon carbonitride (SiCN), a silicon boronitride (SiBN), a silicon borocarbide (SiBC), a silicon boro carbonitride (SiBCN), a boron carbide (BC), a boron nitride (BN), and combinations thereof.

### Claim 3 (depends on 2)

The method of claim 2, wherein the material of the fin template layer is the same material as the fill layer.

### Claim 4 (depends on 1)

The method of claim 1, wherein the fin mesa has a height in a range of about 20 nm to about 100 nm.

### Claim 5 (depends on 4)

The method of claim 4, wherein the elevated substrate tier has a height from the top surface of the substrate in a range of about 10 nm to about 50 nm.

### Claim 6 (depends on 4)

The method of claim 4, wherein the elevated substrate tier forms a step and a ledge on each of the opposite sides of the fin mesa.

### Claim 7 (depends on 6)

The method of claim 6, wherein a first of the ledges extends a distance from the face of the fin mesa in a range of about 5 nm to about 15 nm, and a second of the ledges extends a distance from the face of the fin mesa in a range of about 10 nm to about 50 nm.

### Claim 8 (depends on 7)

The method of claim 7, wherein the dummy fin portion on one of the opposite ends of each of the one or more vertical fins extends over the first ledge, and the dummy fin portion on the other of the opposite ends of each of the one or more vertical fins extends over the second ledge.

### Claim 9 (depends on 8)

The method of claim 8, wherein each of the dummy fin portions extends a distance of about 20 nm to about 100 nm from an endwall of the one or more vertical fins.

### Claim 10

A method of forming a fin field effect transistor, comprising:
forming an elevated substrate tier on a substrate, wherein the elevated substrate tier has a height from the top surface of the substrate in a range of about 10 nm to about 50 nm;
forming a fin mesa on the elevated substrate tier with a fin template layer on the fin mesa, wherein the elevated substrate tier is laterally larger than the fin mesa and fin template layer;
forming a fill layer on the substrate, wherein the fill layer surrounds the fin mesa, elevated substrate tier, and fin template layer;
forming a plurality of fin masks on the top surface of the fill layer and fin template layer, wherein at least one of the plurality of fin masks is over a portion of the fill layer that extends from the surface of the substrate to the bottom surface of the at least one of the plurality of fin masks, and another one of the plurality of fin masks is over the fin mesa; and
removing portions of the fill layer, fin template layer, and fin mesa to form at least one dummy fin from the fill layer, one or more vertical fins from the fin mesa, and a dummy fin portion on each of the opposite ends of each of the one or more vertical fins from the fill layer, wherein each of the dummy fin portions extends a distance of about 20 nm to about 100 nm from an endwall of the one or more vertical fins.

### Claim 11 (depends on 10)

The method of claim 10, wherein a remaining portion of the fill layer forms an isolation region surrounding the elevated substrate tier.

### Claim 12 (depends on 11)

The method of claim 11, wherein the at least one dummy fin is at least two dummy fins where one of the at least two dummy fins is formed on each of the opposite sides of the one or more vertical fins formed from the fin mesa, and wherein the outer sidewalls of the at least two dummy fins face away from other neighboring vertical fins.

### Claim 13 (depends on 12)

The method of claim 12, further comprising forming a bottom spacer layer on the top surfaces of the isolation region and elevated substrate tier; and
forming a gate dielectric layer on the bottom spacer layer, at least two dummy fins, one or more vertical fins, and dummy fin portions.

### Claim 14 (depends on 13)

The method of claim 13, wherein the isolation region, at least two dummy fins, and dummy fin portions are made of silicon nitride (SiN).

### Claim 15 (depends on 14)

The method of claim 14, wherein the one or more vertical fins have a length in a range of about 20 nm to about 200 nm.