# US 10,374,082 B2 · Semiconductor device

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- Number: US 10,374,082 B2
- Document ID: US10374082B2
- Status: Granted
- Kind: B2
- Application number: 15/629,308
- Filed: 2017-06-21
- Published: 2018-01-04
- Granted: 2019-08-06
- Earliest claimed: 2016-06-29
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Yong Don Kim; In Jun Hwang; Jung Han Kang
- Web page: https://patentgrep.com/patent/US10374082B2

## CPC

- H10D 30/65: Lateral DMOS [LDMOS] FETs
- H10D 30/0285: {using formation of insulating sidewall spacers}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/153: {Impurity concentrations or distributions}
- H10D 62/157: {Impurity concentrations or distributions}
- H10D 62/158: {Dispositions}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 62/60: Impurity distributions or concentrations
- H10D 84/0156: {Manufacturing their doped wells}
- H10W 10/031: {of isolation regions comprising PN junctions}
- H10W 10/30: Isolation regions comprising PN junctions
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/371: {Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current}
- H10D 62/378: {Contact regions to the substrate regions}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a substrate of a first conductivity type, a gate electrode on the substrate, a first high concentration impurity region of the first conductivity type that is disposed on a first side of the gate electrode, a first well of the first conductivity type that is disposed under the first high concentration impurity region and surrounds the first high concentration impurity region, a second well of a second conductivity type that overlaps with a portion of the gate electrode and is adjacent to the first well, and a first deep well of the second conductivity type that is disposed under the first well and the second well, the first deep well and the first high concentration impurity region being responsive to a first voltage.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate of a first conductivity type;
a gate electrode on the substrate;
a first high concentration impurity region of the first conductivity type on a first side of the gate electrode;
a first well of the first conductivity type that is under the first high concentration impurity region and surrounds the first high concentration impurity region;
a second well of a second conductivity type that overlaps with a portion of the gate electrode and is adjacent to the first well; and
a first deep well of the second conductivity type that is under the first well and the second well, the first deep well and the first high concentration impurity region being responsive to a first voltage;
a second deep well of the first conductivity type that is between the first well and the first deep well and between the second well and the first deep well;
wherein the second deep well vertically overlaps a first portion of the first well without horizontally overlapping the first well in a cross-sectional view of the semiconductor device, such that a second portion of the first well contacts the first deep well.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, further comprising a second high concentration impurity region of the second conductivity type that is on the first side of the gate electrode,
wherein the second high concentration impurity region is not within the first well, and
the first deep well is connected to the first voltage through the second high concentration impurity region.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, further comprising a second high concentration impurity region of the first conductivity type and a third high concentration impurity region of the second conductivity type that are on a second side of the gate electrode,
wherein the second high concentration impurity region and the third high concentration impurity region are within the second well.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, further comprising a device isolating region that is within the first well between the first high concentration impurity region and the gate electrode,
wherein the gate electrode extends along a portion of an upper surface of the device isolating region.

### Claim 5 (depends on 3)

The semiconductor device of claim 3, wherein the first high concentration impurity region and the second high concentration impurity region are p-type regions, and
the first high concentration impurity region is a drain region and the second high concentration impurity region is a source region.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, further comprising:
a second high concentration impurity region of the second conductivity type that is within the first well between the gate electrode and the first high concentration impurity region; and
a third high concentration impurity region of the second conductivity type that is on a second side of the gate electrode within the second well.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, further comprising a device isolating region that is within the second well between the third high concentration impurity region and the gate electrode,
wherein the gate electrode extends along a portion of an upper surface of the device isolating region.

### Claim 8 (depends on 6)

The semiconductor device of claim 6, wherein the second high concentration impurity region and the third high concentration impurity region are n-type regions, and
the second high concentration impurity region is a source region, and the third high concentration impurity region is a drain region.

### Claim 9 (depends on 6)

The semiconductor device of claim 6, wherein the second high concentration impurity region is responsive to the first voltage.