# US 10,374,081 B2 · Semiconductor switching element

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- Number: US 10,374,081 B2
- Document ID: US10374081B2
- Status: Granted
- Kind: B2
- Application number: 16/075,870
- Filed: 2016-12-26
- Published: 2019-02-21
- Granted: 2019-08-06
- Earliest claimed: 2016-02-26
- Assignees: Toyota Jidosha Kabushiki Kaisha; Denso Corporation
- Applicants: Toyota Jidosha Kabushiki Kaisha; Denso Corporation
- Inventors: Jun Saito; Sachiko Aoi; Yasushi Urakami
- Web page: https://patentgrep.com/patent/US10374081B2

## CPC

- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 12/031: {of IGBTs}
- H10D 12/481: {having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs}
- H10D 30/0297: {using recessing of the gate electrodes, e.g. to form trench gate electrodes}
- H10D 62/107: {Buried supplementary regions, e.g. buried guard rings (multi-RESURF H10D62/111)}
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H10D 62/154: {Dispositions}
- H10D 62/158: {Dispositions}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 62/60: Impurity distributions or concentrations
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 62/8325: {Silicon carbide}
- H10D 64/252: {for vertical or pseudo-vertical devices}
- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D 64/516: {the thicknesses being non-uniform}
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/2042: {into crystalline silicon carbide}
- H10P 30/21: {of electrically active species}
- H10P 30/222: {characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221)}
- H10P 30/28: characterised by an annealing step, e.g. for activation of dopants
- H10D 12/038: {having a recessed gate, e.g. trench-gate IGBTs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A trench gate semiconductor switching element is provided. The semiconductor substrate of this element includes a second conductivity type bottom region in contact with the gate insulation layer at a bottom surface of the trench; and a first conductivity type second semiconductor region extending from a position in contact with a lower surface of the body region to a position in contact with a lower surface of the bottom region, and in contact with the gate insulation layer on a lower side of the body region. The bottom region includes a low concentration region in contact with the gate insulation layer in a first range of the bottom surface positioned at an end in a long direction of the trench; and a high concentration region in contact with the gate insulation layer in a second range of the bottom surface adjacent to the first range.

## Claims

### Claim 1

A switching element comprising:
a semiconductor substrate on an upper surface of which a trench is provided;
a gate insulation layer covering an inner surface of the trench; and
a gate electrode arranged in the trench and insulated from the semiconductor substrate by the gate insulation layer,
wherein the semiconductor substrate comprises:
a first conductivity type first semiconductor region being in contact with the gate insulation layer;
a second conductivity type body region being in contact with the gate insulation layer on a lower side of the first semiconductor region;
a second conductivity type bottom region being in contact with the gate insulation layer at a bottom surface of the trench; and
a first conductivity type second semiconductor region extending from a position being in contact with a lower surface of the body region to a position being in contact with a lower surface of the bottom region, being in contact with the gate insulation layer on a lower side of the body region and separated from the first semiconductor region by the body region, and
the bottom region comprises:
a low concentration region being in contact with the gate insulation layer in a first range of the bottom surface that is positioned at an end in a long direction of the trench; and
a high concentration region being in contact with the gate insulation layer in a second range of the bottom surface that is adjacent to the first range, and a second conductivity type impurity concentration of which being higher than that of the low concentration region.

### Claim 2 (depends on 1)

The switching element according to claim 1, further comprising:
an upper electrode provided on the upper surface of the semiconductor substrate and being in contact with the first semiconductor region,
wherein the semiconductor substrate further comprises a second conductivity type connection region connecting the bottom region and the upper electrode.

### Claim 3 (depends on 1)

The switching element according to claim 1, wherein
the gate insulation layer comprises:
a bottom insulation layer covering the bottom surface of the trench; and
a side insulation layer covering a side surface of the trench and a thickness of which is thinner than that of the bottom insulation layer.

### Claim 4 (depends on 1)

The switching element according to claim 1, wherein
the low concentration region extends from the bottom surface to a first position lower than the bottom surface, and
the high concentration region extends from the bottom surface to a second position lower than the first position.

### Claim 5 (depends on 1)

The switching element according to claim 1, wherein
the semiconductor substrate is constituted of silicon carbide, and
an effective carrier surface density obtained by integrating an effective carrier density in the high concentration region that is located below the trench in a thickness direction of the semiconductor substrate is greater than 1.4×1013 (cm−2).

### Claim 6 (depends on 1)

The switching element according to claim 1, wherein
the semiconductor substrate is constituted of silicon carbide, and
an effective carrier surface density obtained by integrating an effective carrier density in the low concentration region that is located below the trench in a thickness direction of the semiconductor substrate is smaller than 1.4×1013 (cm−2).

### Claim 7 (depends on 1)

The switching element according to claim 1, wherein
the semiconductor substrate is constituted of silicon, and
an effective carrier surface density obtained by integrating an effective carrier density in the high concentration region that is located below the trench in a thickness direction of the semiconductor substrate is greater than 2.0×1012 (cm−2).

### Claim 8 (depends on 1)

The switching element according to claim 1, wherein the semiconductor substrate is constituted of silicon, and
an effective carrier surface density obtained by integrating an effective carrier density in the low concentration region that is located below the trench in a thickness direction of the semiconductor substrate is smaller than 2.0×1012 (cm−2).