# US 10,374,079 B2 · Silicon carbide semiconductor device and method for manufacturing same

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- Number: US 10,374,079 B2
- Document ID: US10374079B2
- Status: Granted
- Kind: B2
- Application number: 15/505,267
- Filed: 2015-09-08
- Published: 2017-09-14
- Granted: 2019-08-06
- Earliest claimed: 2014-09-16
- Assignees: Denso Corporation; Toyota Jidosha Kabushiki Kaisha
- Applicants: Denso Corporation; Toyota Jidosha Kabushiki Kaisha
- Inventors: Hirotaka Saikaku; Jun Sakakibara; Shoji Mizuno; Yuichi Takeuchi
- Web page: https://patentgrep.com/patent/US10374079B2

## CPC

- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 12/031: {of IGBTs}
- H10D 12/038: {having a recessed gate, e.g. trench-gate IGBTs}
- H10D 30/0297: {using recessing of the gate electrodes, e.g. to form trench gate electrodes}
- H10D 62/125: {Shapes of junctions between the regions}
- H10D 62/157: {Impurity concentrations or distributions}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 62/8325: {Silicon carbide}
- H10D 62/159: {Shapes}
- H10P 30/2042: {into crystalline silicon carbide}
- H10P 30/21: {of electrically active species}
- H10P 30/222: {characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A silicon carbide semiconductor device includes: a substrate; a drift layer over the substrate; a base region over the drift layer; multiple source regions over an upper layer portion of the base region; a contact region over the upper layer portion of the base region between opposing source regions; multiple trenches from a surface of each source region to a depth deeper than the base region; a gate electrode on a gate insulating film in each trench; a source electrode electrically connected to the source regions and the contact region; a drain electrode over a rear surface of the substrate; and multiple electric field relaxation layers in the drift layer between adjacent trenches. Each electric field relaxation layer includes: a first region at a position deeper than the trenches; and a second region from a surface of the drift layer to the first region.

## Claims

### Claim 1

A silicon carbide semiconductor device comprising:
a substrate having a first conductivity type or a second conductivity type and made of silicon carbide;
a drift layer disposed over the substrate, made of silicon carbide, and having the first conductivity type with an impurity concentration lower than the substrate;
a base region disposed over the drift layer, made of silicon carbide, and having the second conductivity type;
a plurality of source regions disposed over an upper layer portion of the base region, made of silicon carbide, and having the first conductivity type with an impurity concentration higher than the drift layer;
a contact region disposed over the upper layer portion of the base region between opposing source regions, made of silicon carbide, and having the second conductivity type with an impurity concentration higher than the base layer;
a plurality of trenches disposed from a surface of each source region to a depth deeper than the base region, and arranged in parallel to each other along one direction as a longitudinal direction;
a gate insulating film arranged on an inner wall of each trench;
a gate electrode arranged on the gate insulating film in each trench;
a source electrode electrically connected to the source regions and the contact region;
a drain electrode arranged over a rear surface of the substrate; and
a plurality of electric field relaxation layers disposed in the drift layer located below the base region, spaced apart from a side of each trench, arranged between adjacent trenches along a direction as a longitudinal direction parallel to the longitudinal direction of the trenches, made of silicon carbide, and having the second conductivity type, wherein:
each of the plurality of electric field relaxation layers includes: a first region that is arranged at a position deeper than the trenches; and a second region that is arranged from a surface of the drift layer to the first region and has a uniform impurity concentration;
a distance between adjacent second regions is defined as W1;
a distance between adjacent first regions is defined as W2;
a relationship of “W1>W2” is satisfied;
a width of a trench gate structure, in which the gate insulating film and the gate electrode are disposed in each of the trenches, is defined as W3; and
a relationship of “W2>W3” is satisfied; and
the second regions have an impurity concentration higher than the base region,
wherein:
a portion of the drift layer that is located above the first region surrounds at least a bottom of a trench gate structure and extends across an entire length of the bottom of the trench gate structure, in which the gate insulating film and the gate electrode are disposed in each of the trenches, is a high impurity concentration layer having the impurity concentration of the first conductivity type impurity higher than a remaining portion of the drift layer, and
the second region has the uniform impurity concentration in a depth direction.

### Claim 2 (depends on 1)

The silicon carbide semiconductor device according to claim 1, wherein:
the drift layer has a concave portion at a position corresponding to the second region; and
the second region is an embedded region made of silicon carbide, having the second conductivity type, and embedded in the concave portion.

### Claim 3 (depends on 2)

The silicon carbide semiconductor device according to claim 2, wherein:
the first region is an ion implantation region of an impurity having the second conductivity type under a bottom of the concave portion.

### Claim 4 (depends on 1)

The silicon carbide semiconductor device according to claim 1, wherein:
each of the first region and the second region is an ion implantation region of an impurity having the second conductivity type in the drift layer; and
the ion implantation region of the second region is provided in a box profile of ion implantation.

### Claim 5 (depends on 1)

The silicon carbide semiconductor device according to claim 1, wherein:
a boundary between the high impurity concentration layer and the remaining portion of the drift layer coincides with a boundary between the first region and the second region.

### Claim 6 (depends on 1)

The silicon carbide semiconductor device according to claim 1, wherein:
the high impurity concentration layer extends along a longitudinal direction, which is in parallel to the longitudinal direction of the electric field relaxation layers and the longitudinal direction of the trenches.

### Claim 7 (depends on 1)

The silicon carbide semiconductor device according to claim 1, wherein:
the high impurity concentration layer is configured to reduce a width of a depletion layer extending into the drift layer; and
the high impurity concentration layer is configured to reduce an internal resistance of the drift layer.

### Claim 8 (depends on 1)

The silicon carbide semiconductor device according to claim 1, wherein:
the high impurity concentration layer completely surrounds and extends across an entire width and the entire length of the bottom of each trench.