# US 10,374,077 B2 · Semiconductor device having auxiliary electrode formed in field plate region

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- Number: US 10,374,077 B2
- Document ID: US10374077B2
- Status: Granted
- Kind: B2
- Application number: 15/709,815
- Filed: 2017-09-20
- Published: 2018-03-22
- Granted: 2019-08-06
- Earliest claimed: 2016-09-22
- Assignees: DB HiTek Co., Ltd.
- Applicants: Dongbu Hitek Co., Ltd.
- Inventors: Yong Keon Choi
- Web page: https://patentgrep.com/patent/US10374077B2

## CPC

- H10D 30/665: {having edge termination structures}
- H10D 30/0285: {using formation of insulating sidewall spacers}
- H10D 30/65: Lateral DMOS [LDMOS] FETs
- H10D 30/655: {having edge termination structures}
- H10D 62/104: {having particular shapes of the bodies at or near reverse-biased junctions, e.g. having bevels or moats}
- H10D 62/105: {by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] (IGFETs having LDD or drain extension regions H10D30/601)}
- H10D 62/109: {Reduced surface field [RESURF] PN junction structures}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H10D 64/111: {Field plates}
- H10D 64/112: {comprising multiple field plate segments}
- H10D 64/117: {Recessed field plates, e.g. trench field plates or buried field plates}
- H10D 64/519: {characterised by their top-view geometrical layouts}
- H10D 30/0212: {using self-aligned silicidation}
- H10D 62/157: {Impurity concentrations or distributions}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device includes a source region disposed in a substrate and having a first conductivity type, a drain region disposed in the substrate and having the first conductivity type, a first drift region having the first conductivity type and extending in a channel length direction between the source and drain regions, a second drift region having a second conductivity type and extending parallel to the first drift region, a field plate region disposed in an upper portion of the second drift region, an auxiliary electrode disposed in an upper portion of the field plate region, and a gate electrode disposed on the substrate and electrically connected with the auxiliary electrode. Such devices can reduce the specific on-resistance while also reducing electric field concentrations at the edge portions of the gate electrode, and the breakdown voltage of the device can therefore be significantly improved.

## Claims

### Claim 1

A semiconductor device comprising:
a source region disposed in a substrate and having a first conductivity type;
a drain region disposed in the substrate and having the first conductivity type;
a first drift region having the first conductivity type and extending primarily in a channel length direction between the source and drain regions;
a second drift region having a second conductivity type that is different from the first conductivity type, the second drift region extending primarily parallel to the first drift region, the second drift region defining an upper portion;
a field plate region disposed in the upper portion of the second drift region and the field plate also defining an upper portion;
an auxiliary electrode disposed in the upper portion of the field plate region; and
a gate electrode disposed on the substrate and electrically connected to the auxiliary electrode.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, further comprising a third drift region electrically connected with the first drift region and having the first conductivity type, wherein the drain region is disposed on the third drift region.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein the field plate region extends in the channel length direction, and an end portion of the field plate region is disposed in the third drift region.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, wherein the auxiliary electrode extends adjacent to and parallel the field plate region.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein the gate electrode is disposed directly on a portion of the auxiliary electrode.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, further comprising a body region having the second conductivity type, wherein the source region is disposed on the body region.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, wherein the second drift region is connected with the body region, and the first drift region is spaced apart from the body region.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, further comprising;
a first well region having the first conductivity type; and
a second well region having the second conductivity type and disposed in the first well region,
wherein the first and second drift regions are disposed on the second well region.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, further comprising a silicide blocking layer disposed on the first drift region and the auxiliary electrode.

### Claim 10

A semiconductor device comprising:
a first well region disposed in a substrate and having a first conductivity type;
a second well region disposed in the first well region and having a second conductivity type that is different from the first conductivity type;
a body region disposed on the second well region and having the second conductivity type;
a super junction region disposed on the second well region to be adjacent to the body region and comprising a plurality of first drift regions each having the first conductivity type and a plurality of second drift regions each having the second conductivity type;
a third drift region connected with the first drift regions and having the first conductivity type;
a plurality of field plate regions disposed in upper portions of the second drift regions;
a plurality of auxiliary electrodes each disposed in an upper portion of a corresponding one of the plurality of field plate regions;
a source region disposed in an upper portion of the body region and having the first conductivity type;
a drain region disposed in an upper portion of the third drift region and having the first conductivity type; and
a gate electrode disposed on the substrate and electrically connected with the auxiliary electrode.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, wherein the first and second drift regions extend in a channel length direction between the source and drain regions and are alternately disposed primarily in a channel width direction perpendicular to the channel length direction.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, wherein the field plate regions and the auxiliary electrodes extend along the second drift regions.

### Claim 13 (depends on 12)

The semiconductor device of claim 12, wherein each of the auxiliary electrodes comprises:
a first extending portion connected to the gate electrode and having a first width; and
a second extending portion extending from the first extending portion toward the drain region and having a second width smaller than the first width.

### Claim 14 (depends on 12)

The semiconductor device of claim 12, wherein each of the auxiliary electrodes has a width gradually decreasing from the gate electrode toward the drain region.

### Claim 15 (depends on 11)

The semiconductor device of claim 11, further comprising a silicide blocking layer disposed on the first drift regions and the auxiliary electrodes.

### Claim 16 (depends on 10)

The semiconductor device of claim 10, wherein the auxiliary electrodes are electrically isolated from the first drift regions by the field plate regions.

### Claim 17 (depends on 16)

The semiconductor device of claim 16, wherein side surfaces of the field plate regions are arranged to be in contact with the first drift regions.

### Claim 18 (depends on 10)

The semiconductor device of claim 10, wherein the first drift regions are spaced apart from the body region and the second drift regions are arranged to be in contact with the body region.

### Claim 19 (depends on 10)

The semiconductor device of claim 10, wherein the third drift region is disposed on the first well region.