# US 10,374,073 B2 · Single electron transistor with wrap-around gate

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- Number: US 10,374,073 B2
- Document ID: US10374073B2
- Status: Granted
- Kind: B2
- Application number: 15/623,877
- Filed: 2017-06-15
- Published: 2017-11-02
- Granted: 2019-08-06
- Earliest claimed: 2016-04-28
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Kangguo Cheng; Xin Miao; Wenyu Xu; Chen Zhang
- Web page: https://patentgrep.com/patent/US10374073B2

## CPC

- H10D 30/402: {Single electron transistors; Coulomb blockade transistors}
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 62/118: {Nanostructure semiconductor bodies}
- H10D 62/235: {of IGFETs (IGFETs having buried channels H10D30/637)}
- H10D 62/814: {Quantum box structures}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/512: {Disposition of the gate electrodes, e.g. buried gates}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Transistors and methods of forming the same include forming a fin that has an active layer between two sacrificial layers. Material from the two sacrificial layers is etched away in a region of the fin. A gate stack is formed around the active layer in the region. Source and drain regions are formed in contact with the active layer.

## Claims

### Claim 1

A method for forming a transistor, comprising:
forming a fin comprising an active layer between two sacrificial layers;
etching away material from the two sacrificial layers in a region of the fin;
forming a gate stack around the active layer in the region;
etching the active layer after forming the gate stack to form a quantum dot; and
forming source and drain regions in contact with the active layer.

### Claim 2 (depends on 1)

The method of claim 1, further comprising oxidizing exposed surfaces of the quantum dot to form tunnel barriers, wherein the source and drain regions are in contact with the tunnel barriers.

### Claim 3 (depends on 1)

The method of claim 1, further comprising etching away material from the fin that is not covered by the gate and spacers.

### Claim 4 (depends on 3)

The method of claim 3, wherein etching the active layer further comprises etching away any remaining sacrificial material.

### Claim 5 (depends on 1)

The method of claim 1, further comprising forming a dielectric layer over and around the fin and the gate.

### Claim 6 (depends on 5)

The method of claim 5, further comprising polishing the dielectric layer down to a top level of the gate.

### Claim 7 (depends on 1)

The method of claim 1, wherein forming the gate stack around the active layer comprises conformally forming a gate dielectric layer on surfaces in the region.

### Claim 8 (depends on 7)

The method of claim 7, wherein forming the gate stack around the active layer comprises forming a full wrap-around gate around the active layer.

### Claim 9

A method for forming a transistor, comprising:
forming a fin comprising an active layer between two sacrificial layers;
etching away material from the two sacrificial layers in a first region;
forming a gate stack around the active layer in the first region;
etching the active layer after forming the gate stack to form a quantum dot;
etching away material from the two sacrificial layers outside the first region; and
forming source and drain regions in contact with the active layer in the first region.

### Claim 10 (depends on 9)

The method of claim 9, further comprising oxidizing exposed surfaces of the quantum dot to form tunnel barriers, wherein the source and drain regions are in contact with the tunnel barriers.

### Claim 11 (depends on 9)

The method of claim 9, further comprising forming a dielectric layer over and around the fin and the gate.

### Claim 12 (depends on 11)

The method of claim 11, further comprising polishing the dielectric layer down to a top level of the gate.

### Claim 13 (depends on 9)

The method of claim 9, wherein forming the gate stack around the active layer comprises conformally forming a gate dielectric layer on surfaces in the region.

### Claim 14 (depends on 13)

The method of claim 13, wherein forming the gate stack around the active layer comprises forming a full wrap-around gate around the active layer.

### Claim 15

A transistor, comprising:
a tunnel barrier structure;
a gate stack that wraps fully around the tunnel barrier structure;
a conductive source and drain region, in contact with opposite sides of the tunnel barrier structure, that pass through openings in respective sides of the gate stack.

### Claim 16 (depends on 15)

The transistor of claim 15, wherein the tunnel barrier structure is a conductive quantum dot having insulating tunnel barriers at opposite sides.

### Claim 17 (depends on 16)

The transistor of claim 16, wherein the conductive quantum dot comprises doped silicon and the insulating tunnel barriers comprise oxidized silicon.

### Claim 18 (depends on 15)

The transistor of claim 15, further comprising spacers around an upper portion of the gate stack.