# US 10,374,066 B2 · Fin and shallow trench isolation replacement to prevent gate collapse

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- Number: US 10,374,066 B2
- Document ID: US10374066B2
- Status: Granted
- Kind: B2
- Application number: 15/646,349
- Filed: 2017-07-11
- Published: 2019-01-17
- Granted: 2019-08-06
- Earliest claimed: 2017-07-11
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Soon-Cheon Seo
- Web page: https://patentgrep.com/patent/US10374066B2

## CPC

- H10D 30/0243: {using dummy structures having essentially the same shapes as the semiconductor bodies, e.g. to provide stability}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/834: {comprising FinFETs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor structure and a method for fabricating the same. The structure includes a substrate, active fin structures, and non-active fin structures. The structure further includes isolation regions in contact with the active fin structures, and isolation regions in contact with the non-active fin structures. A first gate structure is in contact with the active fin structures and the isolation regions that are in contact with the active fin structures. A second gate structure is in contact with the non-active fin structures. The method includes forming an isolation region between fin structures. A mask is formed over active fin structures and dummy fin structures are then removed to form a plurality of trenches between the isolation regions. A nitride-based layer is formed in contact with isolation regions corresponding to the dummy fin structures. The nitride-based layer forms a non-active fin structure within each trench of the trenches.

## Claims

### Claim 1

A semiconductor structure comprising at least:
a substrate;
a plurality of active fin structures;
a plurality of non-active fin structures;
a first plurality of isolation regions in contact with the plurality of active fin structures;
a second plurality of isolation regions, wherein the plurality of non-active fin structures is in contact with sidewalls of the second plurality of isolation regions, and wherein non-active fin material contacts a top surface of the non-active plurality of fin structures and the top surface of the second plurality of isolation regions;
a first gate structure in contact with the plurality of active fin structures and the first plurality of isolation regions; and
a second gate structure in contact with a top surface of the non-active fin material extending above a top surface of the second plurality of isolation regions, where the second gate structure is not in contact with the second plurality of isolation regions.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein the plurality of active fin structures and the plurality of non-active fin structures comprise different materials.

### Claim 3 (depends on 1)

The semiconductor structure of claim 1, wherein the first plurality of isolation regions is recessed below a top surface of the plurality of active fin structures.

### Claim 4 (depends on 3)

The semiconductor structure of claim 3, wherein the first plurality of isolation regions is further recessed below a top surface of the second plurality of isolation regions.

### Claim 5 (depends on 1)

The semiconductor structure of claim 1, wherein the plurality of non-active fin structures is part of a non-active fin structure layer formed in contact with a top surface of the second plurality of isolation regions.

### Claim 6 (depends on 5)

The semiconductor structure of claim 5, wherein the second gate structure is formed over and in contact with the non-active fin structure layer.

### Claim 7

An integrated circuit comprising:
a semiconductor structure, wherein the semiconductor structure comprises
a substrate;
a plurality of active fin structures;
a plurality of non-active fin structures;
a first plurality of isolation regions in contact with the plurality of active fin structures;
a second plurality of isolation regions, wherein the plurality of non-active fin structures is in contact with sidewalls of the second plurality of isolation regions, and wherein non-active fin material contacts a top surface of the plurality of non-active fin structures and the top surface of the second plurality of isolation regions;
a first gate structure in contact with the plurality of active fin structures and the first plurality of isolation regions; and
a second gate structure in contact with a top surface of non-active fin material extending above a top surface of the second plurality of isolation regions, where the second gate structure is not in contact with the second plurality of isolation regions.

### Claim 8 (depends on 7)

The integrated circuit of claim 7, wherein the plurality of active fin structures and the plurality of non-active fin structures comprise different materials.

### Claim 9 (depends on 7)

The integrated circuit of claim 7, wherein the first plurality of isolation regions is recessed below a top surface of the plurality of active fin structures.

### Claim 10 (depends on 9)

The integrated circuit of claim 9, wherein the first plurality of isolation regions is further recessed below a top surface of the second plurality of isolation regions.

### Claim 11 (depends on 7)

The integrated circuit of claim 7, wherein the plurality of non-active fin structures is part of a non-active fin structure layer formed in contact with a top surface of the second plurality of isolation regions.

### Claim 12 (depends on 11)

The integrated circuit of claim 11, wherein the second gate structure is formed over and in contact with the non-active fin structure layer.