# US 10,374,065 B2 · Method and device for compound semiconductor fin structure

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- Number: US 10,374,065 B2
- Document ID: US10374065B2
- Status: Granted
- Kind: B2
- Application number: 15/473,164
- Filed: 2017-03-29
- Published: 2017-12-07
- Granted: 2019-08-06
- Earliest claimed: 2016-06-01
- Assignees: Semiconductor Manufacturing International (Shanghai) Corporation; Semiconductor Manufacturing International (Beijing) Corporation
- Applicants: Semiconductor Manufacturing International (Shanghai) Corporation; Semiconductor Manufacturing International (Beijing) Corporation
- Inventors: Haiyang Zhang; Yan Wang
- Web page: https://patentgrep.com/patent/US10374065B2

## CPC

- H10D 30/0243: {using dummy structures having essentially the same shapes as the semiconductor bodies, e.g. to provide stability}
- H10D 30/021: {of FETs having insulated gates [IGFET]}
- H10D 30/026: {having laterally-coplanar source and drain regions, a gate at the sides of the bulk channel, and both horizontal and vertical current flow (of LDMOS H10D30/0289)}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/235: {of IGFETs (IGFETs having buried channels H10D30/637)}
- H10D 62/832: being Group IV materials comprising two or more elements, e.g. SiGe
- H10D 62/85: being Group III-V materials, e.g. GaAs
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 64/018: {Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates}
- H10P 50/242: {of Group IV materials}
- H10B 12/056: {the transistor being a FinFET}
- H10B 12/36: {the transistor being a FinFET}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/611: {having multiple independently-addressable gate electrodes influencing the same channel (FinFETs having multiple distinct gate electrodes H10D30/6215; multi-gate TFT H10D30/6733)}
- H10D 30/6217: {having non-uniform gate electrodes, e.g. gate conductors having varying doping}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/834: {comprising FinFETs}
- H10D 84/853: {comprising FinFETs}
- H10D 86/011: {comprising FinFETs}
- H10D 86/215: {comprising FinFETs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A method of manufacturing a semiconductor device includes forming a first semiconductor layer on a substrate, forming a stack of semiconductor layer structures on the first semiconductor layer, and etching the stack to form a fin structure. Each of the semiconductor layer structures includes a first insulator layer and a second semiconductor layer on the first insulator layer. The first and second semiconductor layers have the same semiconductor compound. The fin structure according to the novel method includes one or more insulator layers to achieve a higher on current/off current ratio, thereby improving the device performance relative to conventional fin structures without the insulator layers.

## Claims

### Claim 1

A method of manufacturing a semiconductor device, comprising:
providing a substrate;
forming a first semiconductor layer on the substrate;
forming a stack of one or more semiconductor layer structures on the first semiconductor layer, each of the semiconductor layer structures including a first insulator layer and a second semiconductor layer on the first insulator layer, the first and second semiconductor layers having a same semiconductor compound;
performing an etching process on the stack of one or more semiconductor layer structures and the first semiconductor layer to form a fin structure; and
forming source and drain regions in the second semiconductor layer and a gate on the fin structure to form a fin-type field effect transistor (FinFET) device.

### Claim 2 (depends on 1)

The method of claim 1, wherein each of the semiconductor layer structures further comprises a third semiconductor layer below the first insulator layer, so that the first insulator layer is between the third semiconductor layer and the second semiconductor layer, the second and third semiconductor layers having at least a common compound element.

### Claim 3 (depends on 2)

The method of claim 2, wherein the second and third semiconductor layers each comprise a group III-V compound.

### Claim 4 (depends on 2)

The method of claim 2, wherein the second semiconductor layer comprises three compound elements, and the third semiconductor layer comprises two compound elements.

### Claim 5 (depends on 2)

The method of claim 2, wherein the third semiconductor layer comprises InP.

### Claim 6 (depends on 1)

The method of claim 1, further comprising forming a fourth semiconductor layer on the substrate, wherein the first semiconductor layer is formed on the fourth semiconductor layer.

### Claim 7 (depends on 6)

The method of claim 6, wherein the fourth semiconductor layer comprises InAlAs.

### Claim 8 (depends on 1)

The method of claim 1, further comprising forming a high-k dielectric layer on the substrate, wherein the first semiconductor layer is formed on the high-k dielectric layer.

### Claim 9 (depends on 1)

The method of claim 1, wherein:
the first semiconductor layer comprises InGaAs;
the second semiconductor layer comprises InGaAs; and
the first insulator layer comprises a high-k dielectric material.

### Claim 10 (depends on 9)

The method of claim 9, wherein the high-k dielectric material comprises HfO2.

### Claim 11 (depends on 1)

The method of claim 1, wherein performing the etching process comprises:
removing a portion of the fin structure to form a trench on opposite sides of the fin structure;
filling the trench with a second insulator layer.

### Claim 12

A method of manufacturing a semiconductor device, comprising:
providing a substrate;
forming a first semiconductor layer on the substrate;
forming a stack of one or more semiconductor layer structures on the first semiconductor layer, each of the semiconductor layer structures including a first insulator layer and a second semiconductor layer on the first insulator layer, the first and second semiconductor layers having a same semiconductor compound;
forming a fourth semiconductor layer on the substrate, wherein the first semiconductor layer is formed on the fourth semiconductor layer; and
performing an etching process on the stack of one or more semiconductor layer structures and the first semiconductor layer to form a fin structure.

### Claim 13 (depends on 12)

The method of claim 12, wherein the fourth semiconductor layer comprises InAlAs.

### Claim 14

A method of manufacturing a semiconductor device, comprising:
providing a substrate;
forming a first semiconductor layer on the substrate;
forming a stack of two or more semiconductor layer structures on the first semiconductor layer, each of the semiconductor layer structures including a first insulator layer and a second semiconductor layer on the first insulator layer, the first and second semiconductor layers having a same semiconductor compound, each of the semiconductor layer structures further comprising a third semiconductor layer below the first insulator layer, so that the first insulator layer is between the third semiconductor layer and the second semiconductor layer;
performing an etching process on the stack of one or more semiconductor layer structures and the first semiconductor layer to form a fin structure.

### Claim 15 (depends on 14)

The method of claim 14, wherein the second and third semiconductor layers have at least a common compound element.