# US 10,374,062 B2 · Array substrate, manufacturing method thereof and display panel

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- Number: US 10,374,062 B2
- Document ID: US10374062B2
- Status: Granted
- Kind: B2
- Application number: 15/519,954
- Filed: 2016-05-23
- Published: 2018-04-05
- Granted: 2019-08-06
- Earliest claimed: 2016-03-09
- Assignees: Boe Technology Group Co., Ltd.; Ordos Yuansheng Optoelectronics Co., Ltd.
- Applicants: Boe Technology Group Co., Ltd.; Ordos Yuansheng Optoelectronics Co., Ltd.
- Inventors: Yanfei Sun
- Web page: https://patentgrep.com/patent/US10374062B2

## CPC

- H10D 30/0314: {of lateral top-gate TFTs comprising only a single gate}
- G02F 1/136227: {Through-hole connection of the pixel electrode to the active element through an insulation layer}
- H10D 30/0321: {comprising silicon, e.g. amorphous silicon or polysilicon}
- H10D 30/6729: {characterised by the electrodes}
- H10D 30/673: {characterised by the shapes, relative sizes or dispositions of the gate electrodes}
- H10D 84/01: Manufacture or treatment
- H10D 86/00: Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D 86/01: Manufacture or treatment
- H10D 86/021: {of multiple TFTs}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/451: {characterised by the compositions or shapes of the interlayer dielectrics}
- H10D 86/60: wherein the TFTs are in active matrices
- H10W 20/082: {the openings being tapered via holes}
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10W 20/48: Insulating materials thereof
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The present invention provides an array substrate, a manufacturing method thereof and a display panel. The array substrate includes a substrate and an insulation layer provided on the substrate, the insulation layer including a via therein formed by etching. The insulation layer further includes a plurality of insulation sub-layers stacked on each other, and an insulation sub-layer among the plurality of insulation sub-layers which is farther away from the substrate has a larger etching rate under an etching condition for forming the via.

## Claims

### Claim 1

An array substrate, comprising a substrate and an insulation layer provided on the substrate, the insulation layer comprising a via therein formed by etching, wherein
the insulation layer comprises a plurality of insulation sub-layers stacked on each other, and an insulation sub-layer among the plurality of insulation sub-layers which is farther away from the substrate has a larger etching rate under an etching condition for forming the via;
each of the plurality of insulation sub-layers is a silicon nitride-containing layer; and
an insulation sub-layer which is farther away from the substrate has a smaller ratio of the number of silicon-nitride bonds to that of silicon-hydrogen bonds.

### Claim 2 (depends on 1)

The array substrate according to claim 1, wherein
the insulation layer consists of a first insulation sub-layer and a second insulation sub-layer provided on a side of the first insulation sub-layer far away from the substrate.

### Claim 3 (depends on 2)

The array substrate according to claim 2, wherein
under the etching condition for forming the via, the first insulation sub-layer has an etching rate ranging from 6000 {acute over (Å)}/min to 7000 {acute over (Å)}/min, and the second insulation sub-layer has an etching rate ranging from 8000 {acute over (Å)}/min to 12000 {acute over (Å)}min.

### Claim 4 (depends on 2)

The array substrate according to claim 2, wherein
a ratio of a thickness of the first insulation sub-layer to that of the second insulation sub-layer is equal to or greater than 4:1.

### Claim 5 (depends on 4)

The array substrate according to claim 4, wherein
the thickness of the first insulation sub-layer ranges from 800 {acute over (Å)} to 1700 {acute over (Å)}, and the thickness of the second insulation sub-layer ranges from 200 {acute over (Å)} to 300 {acute over (Å)}.

### Claim 6 (depends on 1)

The array substrate according to claim 1, wherein the insulation layer is a passivation layer, and
the array substrate further comprises a thin film transistor covered by the insulation layer and located on the substrate, and a pixel electrode provided on a side of the insulation layer far away from the substrate, the pixel electrode being connected to a drain of the thin film transistor through the via in the insulation layer.

### Claim 7

A display panel, comprising an array substrate, which comprises a substrate and an insulation layer provided on the substrate, the insulation layer comprising a via therein formed by etching, wherein
the insulation layer comprises a plurality of insulation sub-layers stacked on each other, and an insulation sub-layer among the plurality of insulation sub-layers which is farther away from the substrate has a larger etching rate under an etching condition for forming the via;
each of the plurality of insulation sub-layers is a silicon nitride-containing layer; and
an insulation sub-layer which is farther away from the substrate has a smaller ratio of the number of silicon-nitride bonds to that of silicon-hydrogen bonds.

### Claim 8

A manufacturing method of an array substrate, comprising steps of
forming a plurality of insulation sub-layers stacked on each other on a substrate sequentially, so that the plurality of insulation sub-layers form an insulation layer, and an insulation sub-layer among the plurality of insulation sub-layers which is farther away from the substrate has a larger etching rate; and
etching the plurality of insulation sub-layers of the insulation layer to form a via, under a same etching condition;
wherein each of the plurality of insulation sub-layers is a silicon nitride-containing layer, and an insulation sub-layer which is farther away from the substrate has a smaller ratio of the number of silicon-nitride bonds to that of silicon-hydrogen bonds.

### Claim 9 (depends on 8)

The manufacturing method according to claim 8, wherein, each of the plurality of insulation sub-layers is formed by a plasma-enhanced chemical vapor deposition process, wherein a mixed gas of silane and ammonia gas is used as a process gas, and the plurality of insulation sub-layers are formed under at least one of the following conditions:
C1: when an insulation sub-layer which is farther away from the substrate is formed, a flow amount of silane, a flow amount of ammonia gas and a ratio of the flow amount of silane to the flow amount of ammonia gas are smaller; and
C2: when an insulation sub-layer which is farther away from the substrate is formed, a radio frequency power of plasma is smaller.

### Claim 10 (depends on 7)

The display panel according to claim 7, wherein
the insulation layer consists of a first insulation sub-layer and a second insulation sub-layer provided on a side of the first insulation sub-layer far away from the substrate.

### Claim 11 (depends on 10)

The display panel according to claim 10, wherein
under the etching condition for forming the via, the first insulation sub-layer has an etching rate ranging from 6000 {acute over (Å)}/min to 7000 {acute over (Å)}/min, and the second insulation sub-layer has an etching rate ranging from 8000 {acute over (Å)}/min to 12000 {acute over (Å)}/min.

### Claim 12 (depends on 10)

The display panel according to claim 10, wherein
a ratio of a thickness of the first insulation sub-layer to that of the second insulation sub-layer is equal to or greater than 4:1.

### Claim 13 (depends on 12)

The display panel according to claim 12, wherein
the thickness of the first insulation sub-layer ranges from 800 {acute over (Å)} to 1700 {acute over (Å)}, and the thickness of the second insulation sub-layer ranges from 200 {acute over (Å)} to 300 {acute over (Å)}.

### Claim 14 (depends on 7)

The display panel according to claim 7, wherein the insulation layer is a passivation layer, and
the array substrate further comprises a thin film transistor covered by the insulation layer and located on the substrate, and a pixel electrode provided on a side of the insulation layer far away from the substrate, the pixel electrode being connected to a drain of the thin film transistor through the via in the insulation layer.