# US 10,374,059 B2 · Structure and formation method of semiconductor device structure with nanowires

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- Number: US 10,374,059 B2
- Document ID: US10374059B2
- Status: Granted
- Kind: B2
- Application number: 15/692,124
- Filed: 2017-08-31
- Published: 2019-02-28
- Granted: 2019-08-06
- Earliest claimed: 2017-08-31
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Chao-Ching Cheng; Wei-Sheng Yun; Shao-Ming Yu; Tsung-Lin Lee; Chih-Chieh Yeh
- Web page: https://patentgrep.com/patent/US10374059B2

## CPC

- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/122: {oriented at angles to substrates, e.g. perpendicular to substrates}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/01: Manufacture or treatment
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/251: {Source or drain electrodes for field-effect devices}
- H10D 64/512: {Disposition of the gate electrodes, e.g. buried gates}
- H10D 64/514: {characterised by the insulating layers}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 84/853: {comprising FinFETs}
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10D 88/01: {Manufacture or treatment}
- H10W 10/0121: {in regions recessed from the surface, e.g. in trenches or grooves}
- H10W 10/13: formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Structures and formation methods of a semiconductor device structure are provided. The method includes providing a substrate having a base portion and a fin portion over the base portion. The fin portion has a channel region and a source/drain region. The method also includes forming a stack structure over the fin portion. The stack structure includes first and second semiconductor layers. The method also includes forming a source/drain portion in the stack structure at the source/drain region, and removing a portion of the second semiconductor layer in the channel region in an etching process. The remaining portion of the first semiconductor layer in the channel region forms a nanowire. The method further includes forming a gate dielectric layer surrounding the nanowire, forming a high-k dielectric layer surrounding the gate dielectric layer, and forming a gate electrode surrounding the high-k dielectric layer.

## Claims

### Claim 1

A method for forming a semiconductor device structure,
comprising:
providing a substrate having a base portion and a fin portion over the base portion, wherein the fin portion has a channel region and a source/drain region;
forming a stack structure over the fin portion, wherein the stack structure comprises a first semiconductor layer and a second semiconductor layer vertically stacked over the fin portion;
forming a first protective layer covering the stack structure;
forming a source/drain portion in the stack structure at the source/drain region, wherein the first protective layer is formed before forming the source/drain portion;
removing a portion of the second semiconductor layer in the channel region in an etching process, wherein a remaining portion of the first semiconductor layer in the channel region forms a nanowire;
forming a gate dielectric layer surrounding the nanowire;
forming a high-k dielectric layer surrounding the gate dielectric layer; and
forming a gate electrode surrounding the high-k dielectric layer.

### Claim 2 (depends on 1)

The method as claimed in claim 1, wherein the semiconductor device structure has an input-output region and a core region, wherein the nanowire surrounded by the gate dielectric layer is positioned in the input-output region.

### Claim 3 (depends on 1)

The method as claimed in claim 1, wherein after formation of the gate dielectric layer, the method further comprises:
performing an annealing process on the gate dielectric layer.

### Claim 4 (depends on 1)

The method as claimed in claim 1
wherein before removing the portion of the second semiconductor layer in the channel region, the method further comprises:
removing the first protective layer in the channel region.

### Claim 5 (depends on 1)

The method as claimed in claim 1, wherein after formation of the nanowire, the method further comprises:
forming a second protective layer surrounding the nanowire in the channel region, wherein the gate dielectric layer surrounds the second protective layer.

### Claim 6 (depends on 5)

The method as claimed in claim 5, wherein before forming the high-k dielectric layer, the method further comprises:
forming an additional layer surrounding the gate dielectric layer, wherein the high-k dielectric layer surrounds the additional layer.

### Claim 7 (depends on 1)

The method as claimed in claim 1, wherein the stack structure comprises a plurality of the first semiconductor layers and a plurality of the second semiconductor layers alternately stacked vertically over the fin portion,
wherein the etching process removes portions of the plurality of the second semiconductor layers in the channel region, and the remaining portions of the plurality of the first semiconductor layers in the channel region form a plurality of the nanowires.

### Claim 8 (depends on 7)

The method as claimed in claim 7, wherein the nanowires are vertically spaced apart from each other by a first distance, wherein the first distance is substantially equal to a thickness of the second semiconductor layer.

### Claim 9 (depends on 1)

The method as claimed in claim 1, wherein a thickness of the first semiconductor layer is substantially equal to a thickness of the second semiconductor layer.

### Claim 10 (depends on 1)

The method as claimed in claim 1, wherein the etching process further removes an upper portion of the fin portion of the substrate.

### Claim 11

A method for forming a semiconductor device structure, comprising:
forming a first stack structure over a first fin portion in an input-output region of a substrate and a second stack structure over a second fin portion in a core region of the substrate;
forming a first source/drain portion in the first stack structure and a second source/drain portion in the second stack structure;
removing a portion of the first stack structure to form a first nanowire in the input-output region;
removing a portion of the second stack structure to form a second nanowire in the core region;
forming a dielectric layer surrounding the first nanowire;
annealing the dielectric layer after the first nanowire is formed;
forming a first gate structure surrounding the dielectric layer and the first nanowire, wherein the first gate structure is adjacent to the first source/drain portion; and
forming a second gate structure surrounding the second nanowire, wherein the second gate structure is adjacent to the second source/drain portion.

### Claim 12 (depends on 11)

The method as claimed in claim 11, further comprising:
forming a first protective layer between the dielectric layer and the first nanowire; and
forming a second protective layer between the second gate structure and the second nanowire.

### Claim 13 (depends on 12)

The method as claimed in claim 12, further comprising:
forming a second additional layer between the second protective layer and the second gate structure in the core region.

### Claim 14 (depends on 13)

The method as claimed in claim 13, further comprising:
forming a high-k dielectric layer surrounding the dielectric layer, wherein the second additional layer is surrounded by the high-k dielectric layer in the core region.

### Claim 15 (depends on 11)

The method as claimed in claim 11, further comprising:
forming a first additional layer between the dielectric layer and the first gate structure in the input-output region.

### Claim 16

A method for forming a semiconductor device structure, comprising:
forming a stack structure over a substrate;
forming a dummy gate structure over the stack structure, wherein the dummy gate structure has a dummy gate dielectric layer and a dummy gate electrode over the gate dielectric layer;
forming a source/drain portion in the stack structure;
forming an interlayer dielectric layer over the source/drain portion;
forming a protective element over the interlayer dielectric layer;
removing a portion of the stack structure to form a nanowire; and
replacing the dummy gate structure with a gate structure, wherein the gate structure has a gate electrode and a gate dielectric layer surrounded by the gate electrode, the gate dielectric and the gate dielectric layer is thicker than the dummy gate dielectric layer, and
wherein the nanowire is surrounded by the gate structure.

### Claim 17 (depends on 16)

The method as claimed in claim 16, further comprising:
removing a portion of the interlayer dielectric layer, wherein the protective element is formed over a remaining portion of the interlayer dielectric layer, and the protective element is formed before the nanowire.

### Claim 18 (depends on 16)

The method as claimed in claim 16, further comprising:
forming an etch stop layer over the source/drain portion, wherein the interlayer dielectric layer is above the etch stop layer, and the protective element is disposed between two sidewalls of the etch stop layer.

### Claim 19 (depends on 16)

The method as claimed in claim 16, wherein a material of the protective element is different from a material of the interlayer dielectric layer.

### Claim 20 (depends on 16)

The method as claimed in claim 16, further comprising:
forming a protective layer between the nanowire and the gate structure; and
performing a clean process before forming the protective layer, wherein the interlayer dielectric layer is protected by the protective element during the clean process.