# US 10,374,058 B2 · Semiconductor device and method for manufacturing the same

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- Number: US 10,374,058 B2
- Document ID: US10374058B2
- Status: Granted
- Kind: B2
- Application number: 15/706,456
- Filed: 2017-09-15
- Published: 2019-03-21
- Granted: 2019-08-06
- Earliest claimed: 2017-09-15
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Huan-Chieh Su; Zhi-Chang Lin; Ting-Hung Hsu; Jia-Ni Yu; Wei-Hao Wu; Chih-Hao Wang
- Web page: https://patentgrep.com/patent/US10374058B2

## CPC

- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 30/0243: {using dummy structures having essentially the same shapes as the semiconductor bodies, e.g. to provide stability}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 64/669: {the conductor further comprising additional layers of alloy material, compound material or organic material, e.g. TaN/TiAlN}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/014: {the gate conductors having different materials or different implants}
- H10D 84/0142: {the gate conductors having different shapes or dimensions}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 84/83135: {the IGFETs characterised by having different gate conductor materials or different gate conductor implants}
- H10D 84/83138: {the IGFETs characterised by having different shapes or dimensions of their gate conductors}
- H10D 84/834: {comprising FinFETs}
- H10D 84/853: {comprising FinFETs}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method for manufacturing a semiconductor device is provided. The method for manufacturing a semiconductor device includes forming a gate electrode layer in a gate trench; filling a recess in the gate electrode layer with a dielectric feature; and etching back the gate electrode layer from top end surfaces of the gate electrode layer while leaving a portion of the gate electrode layer under the dielectric feature.

## Claims

### Claim 1

A semiconductor device, comprising:
a semiconductor substrate;
a plurality of gate spacers over the semiconductor substrate;
a gate electrode between the gate spacers;
a first dielectric feature between the gate spacers and in contact with a top surface of the gate electrode; and
a second dielectric feature between the first dielectric feature and one of the gate spacers, wherein a sidewall of the first dielectric feature is at least partially separated from the second dielectric feature, wherein the gate electrode comprises a gate conductor and a work function conductor surrounding the gate conductor, the gate conductor is in contact with the first dielectric feature, and the work function conductor is separated from the first dielectric feature.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, further comprising:
a plurality of semiconductor fins over the semiconductor substrate; and
a dummy fin between the semiconductor fins, wherein the gate electrode extends across the semiconductor fins and the dummy fin.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein the first dielectric feature extends across the semiconductor fins and the dummy fin.

### Claim 4 (depends on 2)

The semiconductor device of claim 2, further comprising:
a gate contact via over the dummy fin and connected to the gate electrode.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, further comprising:
a gate contact via in the first dielectric feature and connected to the gate electrode.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the work function conductor is in contact with the second dielectric feature.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the gate conductor has a portion between the first dielectric feature and the second dielectric feature.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein a top surface of the first dielectric feature and a top surface of the second dielectric feature are coplanar.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein the first dielectric feature comprises a material the same as that of the second dielectric feature.

### Claim 10 (depends on 1)

The semiconductor device of claim 1, wherein the gate conductor is in contact with the sidewall of the first dielectric feature.

### Claim 11 (depends on 1)

The semiconductor device of claim 1, wherein a bottom surface of the second dielectric feature is over the top surface of the gate electrode.

### Claim 12

A semiconductor device, comprising:
a semiconductor substrate;
a plurality of gate spacers over the semiconductor substrate;
a gate conductor between the gate spacers;
a work function conductor surrounding the gate conductor; and
a first dielectric feature between the gate spacers and over the gate conductor, wherein the first dielectric feature is separated from the work function conductor and the gate conductor has a first portion higher than a bottom surface of the first dielectric feature.

### Claim 13 (depends on 12)

The semiconductor device of claim 12, further comprising:
a second dielectric feature over the work function conductor and surrounding the first dielectric feature.

### Claim 14 (depends on 13)

The semiconductor device of claim 13, wherein the first portion of the gate conductor is between the first dielectric feature and the second dielectric feature.

### Claim 15 (depends on 14)

The semiconductor device of claim 14, wherein the gate conductor has a second portion between the first dielectric feature and the work function conductor, and the second portion of the gate conductor is connected with the first portion of the gate conductor.

### Claim 16

A semiconductor device, comprising:
a semiconductor substrate;
a plurality of first gate spacers over the semiconductor substrate;
a first gate electrode between the first gate spacers; and
a first dielectric feature between the first gate spacers and over the first gate electrode; and
a second dielectric feature separating the first dielectric feature from the first gate spacers, wherein a bottom surface of the second dielectric feature is in contact with a top surface of the first gate electrode.

### Claim 17 (depends on 16)

The semiconductor device of claim 16, further comprising:
a plurality of second gate spacers over the semiconductor substrate;
a second gate electrode between the second gate spacers; and
a third dielectric feature between the second gate spacers and over the second gate electrode, wherein the third dielectric feature is in contact with the second gate spacers.

### Claim 18 (depends on 17)

The semiconductor device of claim 17, wherein a distance between the first gate spacers is greater than a distance between the second gate spacers.

### Claim 19 (depends on 17)

The semiconductor device of claim 17, wherein the third dielectric feature covers the second gate electrode.

### Claim 20 (depends on 16)

The semiconductor device of claim 16, wherein the first gate electrode surrounds the first dielectric feature.