# US 10,374,055 B2 · Buffer layer on semiconductor devices

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- Number: US 10,374,055 B2
- Document ID: US10374055B2
- Status: Granted
- Kind: B2
- Application number: 14/303,045
- Filed: 2014-06-12
- Published: 2014-10-02
- Granted: 2019-08-06
- Earliest claimed: 2011-08-01
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Cheng-Hao Hou; Wei-Yang Lee; Xiong-Fei Yu; Kuang-Yuan Hsu
- Web page: https://patentgrep.com/patent/US10374055B2

## CPC

- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D 64/01318: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314)}
- H10D 64/664: {the additional layers comprising a barrier layer between the layer of silicon and an upper metal or metal silicide layer}
- H10D 64/665: {the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum (having lateral variation H10D64/671)}
- H10D 64/666: {the conductor further comprising additional layers}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 64/669: {the conductor further comprising additional layers of alloy material, compound material or organic material, e.g. TaN/TiAlN}
- H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)}
- H10D 64/685: {being perpendicular to the channel plane}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device including a substrate having a source region, a drain region, and a channel region disposed between the source region and the drain region. Additionally, the semiconductor device includes a high-k dielectric layer formed over the channel region, an n-metal formed over the high-k dielectric layer and a barrier layer formed between the high-k dielectric layer and the n-metal, the barrier layer including a layer of annealed silicon.

## Claims

### Claim 1

A semiconductor device comprising:
a substrate having a source region, a drain region, and a channel region disposed between the source region and the drain region;
a high-k dielectric layer over the channel region;
an n-metal over the high-k dielectric layer, wherein the n-metal is free of silicon; and
a barrier layer between the high-k dielectric layer and the n-metal, the barrier layer comprising:
a layer of titanium silicide alloy,
a first layer of titanium nitride,
a second layer of titanium nitride, wherein the layer of titanium silicide alloy is between the first layer of titanium nitride and the second layer of titanium nitride, and
a silicon layer between the second layer of titanium nitride and the layer of titanium silicide alloy.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the second layer of titanium nitride is between the n-metal and the layer of titanium silicide alloy.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the high-k dielectric layer comprises at least one of hafnium oxide, zirconium, aluminum oxide, tantalum oxide, indium oxide, lanthanum oxide, hafnium silicon oxynitride, hafnium tantalum oxide, or strontium oxide.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the n-metal comprises at least one of hafnium, zirconium, titanium, aluminum, or metal carbide.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the high-k dielectric layer has a thickness ranging from about 1 nm to about 4 nm.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the source region and the drain region comprise lightly doped regions.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the barrier layer is between sidewalls of the n-metal and sidewalls of the high-k dielectric layer.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein an upper-most surface of the n-metal has a width greater than a width of a bottommost surface of the n-metal.

### Claim 9

A semiconductor device comprising:
a high-k dielectric layer over a substrate;
a first titanium nitride layer over the high-k dielectric layer;
a titanium silicide alloy layer on the first titanium nitride layer;
an n-metal over the high-k dielectric layer;
a second titanium nitride layer between the titanium silicide alloy layer and the n-metal; and
a silicon layer between the second titanium nitride layer and the titanium silicide alloy layer.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein the n-metal comprises at least one of hafnium, zirconium, titanium, aluminum, or metal carbide.

### Claim 11 (depends on 9)

The semiconductor device of claim 9, wherein the high-k dielectric layer has a thickness ranging from about 1 nm to about 4 nm.

### Claim 12 (depends on 9)

The semiconductor device of claim 9, wherein the second titanium nitride layer is between sidewalls of the n-metal and sidewalls of the high-k dielectric layer.

### Claim 13 (depends on 9)

The semiconductor device of claim 9, wherein a top-most surface of the first titanium nitride layer is co-planar with a top-most surface of the second titanium nitride layer.

### Claim 14 (depends on 9)

The semiconductor device of claim 9, wherein an upper-most surface of the n-metal has a width greater than a width of a bottommost surface of the n-metal.

### Claim 15

A semiconductor device comprising:
a gate dielectric layer over a substrate;
a cap barrier layer over the gate dielectric layer, wherein the cap barrier layer comprises titanium nitride;
a silicide alloy layer between the cap barrier layer and the gate dielectric;
a lower barrier layer between the gate dielectric layer and the silicide alloy layer;
a silicon layer over the silicide alloy layer;
an n-metal over the silicon layer, wherein an upper-most surface of the n-metal has a width greater than a width of a bottommost surface of the n-metal; and
a spacer surrounding the gate dielectric layer, wherein a top surface of the spacer is substantially coplanar with a top surface of the cap barrier.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, wherein the gate dielectric layer has a thickness ranging from about 1 nm to about 4 nm.

### Claim 17 (depends on 15)

The semiconductor device of claim 15, wherein the n-metal comprises at least one of hafnium, zirconium, titanium, aluminum, or metal carbide.

### Claim 18 (depends on 15)

The semiconductor device of claim 15, wherein the gate dielectric layer comprises at least one of hafnium oxide, zirconium, aluminum oxide, tantalum oxide, indium oxide, lanthanum oxide, hafnium silicon oxynitride, hafnium tantalum oxide, or strontium oxide.

### Claim 19 (depends on 15)

The semiconductor device of claim 15, wherein the cap barrier layer is between sidewalls of the n-metal and sidewalls of the gate dielectric layer.

### Claim 20 (depends on 15)

The semiconductor device of claim 15, wherein a top-most surface of the lower barrier layer is co-planar with a top-most surface of the cap barrier layer.