# US 10,374,054 B2 · Ferroelectric memory devices

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- Number: US 10,374,054 B2
- Document ID: US10374054B2
- Status: Granted
- Kind: B2
- Application number: 15/987,898
- Filed: 2018-05-24
- Published: 2018-12-27
- Granted: 2019-08-06
- Earliest claimed: 2017-06-27
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Hyangkeun Yoo
- Web page: https://patentgrep.com/patent/US10374054B2

## CPC

- H10D 64/689: {having ferroelectric layers}
- G11C 11/223: {using MOS with ferroelectric gate insulating film}
- H10D 30/0415: {of FETs having ferroelectric gate insulators}
- H10D 30/701: {IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs}
- H10D 64/033: {comprising ferroelectric layers}
- H10D 64/685: {being perpendicular to the channel plane}
- G11C 11/2275: {Writing or programming circuits or methods}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A ferroelectric memory device includes a substrate having a source electrode and a drain electrode therein, a first interfacial dielectric layer including an anti-ferroelectric material disposed on the substrate between the source electrode and the drain electrode, a ferroelectric gate dielectric layer including a ferroelectric material disposed on the first interfacial dielectric layer, and a gate electrode disposed on the ferroelectric gate dielectric layer.

## Claims

### Claim 1

A ferroelectric memory device comprising:
a substrate having a source electrode and a drain electrode;
a first interfacial dielectric layer including an anti-ferroelectric material disposed on the substrate between the source electrode and the drain electrode;
a ferroelectric gate dielectric layer including a ferroelectric material disposed on the first interfacial dielectric; and
a gate electrode disposed on the ferroelectric gate dielectric layer,
wherein lattice constants of the first interfacial dielectric layer is substantially identical to lattice constants of the ferroelectric gate dielectric layer.

### Claim 2 (depends on 1)

The ferroelectric memory device of claim 1, wherein the first interfacial dielectric layer includes at least one of a hafnium oxide material, a zirconium oxide material and a hafnium zirconium oxide material.

### Claim 3 (depends on 1)

The ferroelectric memory device of claim 1, wherein the ferroelectric gate dielectric layer includes at least one of a hafnium oxide material, a zirconium oxide material and a hafnium zirconium oxide material.

### Claim 4 (depends on 1)

The ferroelectric memory device of claim 1,
wherein the ferroelectric gate dielectric layer is doped with dopants; and
wherein the dopants include at least one element of carbon (C), silicon (Si), magnesium (Mg), aluminum (Al), yttrium (Y), nitrogen (N), germanium (Ge), tin (Sn), strontium (Sr), lead (Pb), calcium (Ca), barium (Ba), titanium (Ti), zirconium (Zr), gadolinium (Gd) and lanthanum (La).

### Claim 5 (depends on 1)

The ferroelectric memory device of claim 1, further comprising an insulation layer disposed between the substrate and the first interfacial dielectric layer,
wherein the insulation layer incudes at least one of a silicon oxide material, a silicon nitride material, a silicon oxynitride material and an aluminum oxide material.

### Claim 6 (depends on 1)

The ferroelectric memory device of claim 1, wherein the gate electrode includes at least one of a tungsten (W) material, a titanium (Ti) material, a copper (Cu) material, an aluminum (Al) material, a platinum (Pt) material, an iridium (Ir) material, a ruthenium (Ru) material, a tungsten nitride (WN) material, a titanium nitride (TiN) material, a tantalum nitride (TaN) material, an iridium oxide (IrO) material, a ruthenium oxide (RuO) material, a tungsten carbide (WC) material, a titanium carbide (TiC) material, a tungsten silicide (WSi) material, a titanium silicide (TiSi) material and a tantalum silicide (TaSi) material.

### Claim 7 (depends on 1)

The ferroelectric memory device of claim 1, further comprising a second interfacial dielectric layer disposed between the ferroelectric gate dielectric layer and the gate electrode,
wherein the second interfacial dielectric layer includes a metal oxide material having a para-electric property or an anti-ferroelectric property.

### Claim 8 (depends on 7)

The ferroelectric memory device of claim 7, wherein the second interfacial dielectric layer has a bandgap energy which is greater than a bandgap energy of the ferroelectric gate dielectric layer.

### Claim 9 (depends on 7)

The ferroelectric memory device of claim 7, further comprising a third interfacial dielectric layer disposed between the ferroelectric gate dielectric layer and the second interfacial dielectric layer,
wherein lattice constants of the ferroelectric gate dielectric layer are substantially identical to lattice constants of the third interfacial dielectric layer.

### Claim 10

A ferroelectric memory device comprising:
a semiconductor substrate;
an insulation layer disposed on the semiconductor substrate;
a first interfacial dielectric layer including an anti-ferroelectric material disposed on the insulation layer;
a ferroelectric gate dielectric layer including a ferroelectric material disposed on the first interfacial dielectric; and
a gate electrode disposed on the ferroelectric gate dielectric layer,
wherein the first interfacial dielectric layer has a dielectric constant which is greater than a dielectric constant of the insulation layer, and
wherein lattice constants of the first interfacial dielectric layer are substantially identical to lattice constants of the ferroelectric gate dielectric layer.

### Claim 11 (depends on 10)

The ferroelectric memory device of claim 10, wherein the insulation layer incudes at least one of a silicon oxide material, a silicon nitride material, a silicon oxynitride material and an aluminum oxide material.

### Claim 12 (depends on 10)

The ferroelectric memory device of claim 10, wherein the first interfacial dielectric layer includes at least one of a hafnium oxide material, a zirconium oxide material and a hafnium zirconium oxide material.

### Claim 13 (depends on 10)

The ferroelectric memory device of claim 10, wherein the ferroelectric gate dielectric layer includes at least one of a hafnium oxide material, a zirconium oxide material and a hafnium zirconium oxide material.

### Claim 14 (depends on 10)

The ferroelectric memory device of claim 10, further comprising a second interfacial dielectric layer and a third interfacial dielectric layer which are disposed between the ferroelectric gate dielectric layer and the gate electrode,
wherein the second interfacial dielectric layer and the third interfacial dielectric layer have a para-electric or an anti-ferroelectric properties.

### Claim 15 (depends on 14)

The ferroelectric memory device of claim 14, wherein the second interfacial dielectric layer has a bandgap energy which is greater than a bandgap energy of the ferroelectric gate dielectric layer.

### Claim 16 (depends on 15)

The ferroelectric memory device of claim 15,
wherein the third interfacial dielectric layer is disposed between the ferroelectric gate dielectric layer and the second interfacial dielectric layer; and
wherein lattice constants of the third interfacial dielectric layer are substantially identical to lattice constants of the ferroelectric gate dielectric layer.

### Claim 17 (depends on 10)

The ferroelectric memory device of claim 10, wherein the gate electrode includes at least one of a tungsten (W) material, a titanium (Ti) material, a copper (Cu) material, an aluminum (Al) material, a platinum (Pt) material, an iridium (Ir) material, a ruthenium (Ru) material, a tungsten nitride (WN) material, a titanium nitride (TiN) material, a tantalum nitride (TaN) material, an iridium oxide (IrO) material, a ruthenium oxide (RuO) material, a tungsten carbide (WC) material, a titanium carbide (TiC) material, a tungsten silicide (WSi) material, a titanium silicide (TiSi) material and a tantalum silicide (TaSi) material.

### Claim 18 (depends on 10)

The ferroelectric memory device of claim 10, further comprising a source electrode and a drain electrode disposed in the semiconductor substrate,
wherein the insulation layer is disposed on a channel region located in the substrate and between the source electrode and the drain electrode.

### Claim 19 (depends on 18)

The ferroelectric memory device of claim 18, wherein the source electrode and the drain electrode have a conductivity type which is different from a conductivity type of the semiconductor substrate.