# US 10,374,053 B2 · Semiconductor device and manufacturing method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,374,053 B2 - Document ID: US10374053B2 - Status: Granted - Kind: B2 - Application number: 15/513,545 - Filed: 2015-03-30 - Published: 2017-11-02 - Granted: 2019-08-06 - Earliest claimed: 2015-03-30 - Assignees: Renesas Electronics Corporation - Applicants: Renesas Electronics Corporation - Inventors: Yoshitake Kato - Web page: https://patentgrep.com/patent/US10374053B2 ## CPC - H10D 64/685: {being perpendicular to the channel plane} - H10D 30/475: {having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs} - H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN} - H10D 64/011: {of electrodes ohmically coupled to a semiconductor} - H10D 64/01358: {the insulator being formed after the semiconductor body, the semiconductor being a Group III-V material} - H10D 64/118: {Electrodes comprising insulating layers having particular dielectric or electrostatic properties, e.g. having static charges} - H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates} - H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)} - H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)} - H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT} - H10D 30/021: {of FETs having insulated gates [IGFET]} - H10D 30/4755: {having wide bandgap charge-carrier supplying layers, e.g. modulation doped HEMTs such as n-AlGaAs/GaAs HEMTs} - H10D 64/519: {characterised by their top-view geometrical layouts} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract The characteristics of a semiconductor device are enhanced. In a semiconductor device (MISFET) having a gate electrode GE formed on a nitride semiconductor layer CH via a gate insulating film GI, the gate insulating film GI is configured to have a first gate insulating film (oxide film of a first metal) GIa formed on the nitride semiconductor layer CH and a second gate insulating film (oxide film of a second metal) GIb. And, the second metal (e.g., Hf) has lower electronegativity than the first metal (e.g., Al). By thus making the electronegativity of the second metal lower than the electronegativity of the first metal, a threshold voltage (Vth) can be shifted in a positive direction. Moreover, the gate electrode GE is configured to have a first gate electrode (nitride film of a third metal) GEa formed on the second gate insulating film GIb and a second gate electrode (fourth metal) GEb. This prevents the diffusion of oxygen to the gate insulating film GI, and variations in the threshold voltage (Vth) can be reduced. ## Claims ### Claim 1 A semiconductor device comprising: a nitride semiconductor layer; a first gate insulating film provided on the nitride semiconductor layer; a second gate insulating film provided on the first gate insulating film; a first gate electrode formed on a surface of the second gate insulating film and contacting the surface of the second gate insulating film; and a second gate electrode provided on a surface of the first gate electrode and contacting the surface of the first gate electrode, wherein the first gate insulating film is an oxide film containing a first metal or an oxide film containing silicon, the second gate insulating film is an oxide film containing a second metal, an electronegativity of the second metal is smaller than that of the first metal or silicon, the first gate electrode is a nitride film containing a third metal, and the second gate electrode is formed of a fourth metal, and wherein the nitride film containing the third metal comprises titanium nitride having a ratio (N/Ti) of nitrogen (N) to titanium (Ti) which is greater than 1. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein the first metal is Al. ### Claim 3 (depends on 2) The semiconductor device according to claim 2, wherein the second metal is one or more elements selected from a group of Hf, Zr, Ta, Ti, Nb, La, Y and Mg. ### Claim 4 (depends on 1) The semiconductor device according to claim 1, wherein the fourth metal is W. ### Claim 5 (depends on 4) The semiconductor device according to claim 4, wherein a film thickness of the second gate electrode is 50 nm or more. ### Claim 6 (depends on 4) The semiconductor device according to claim 4, wherein the second gate electrode covers an entirety of an upper surface of the first gate electrode. ### Claim 7 (depends on 4) The semiconductor device according to claim 4, wherein the nitride semiconductor layer is GaN. ### Claim 8 (depends on 4) The semiconductor device according to claim 4 further comprising: a third gate insulating film between the nitride semiconductor layer and the first gate insulating film, wherein the third gate insulating film is a silicon oxide film or a silicon nitride film. ### Claim 9 (depends on 1) The semiconductor device according to claim 1, wherein the first gate insulating film is formed on a surface of the nitride semiconductor layer and contacts the surface of the nitride semiconductor layer, and wherein the second gate insulating film is formed on a surface of the first gate insulating film and contacts a surface of the first gate insulating film. ### Claim 10 (depends on 1) The semiconductor device according to claim 1, wherein a thickness of the second gate insulating film is less than a thickness of the first gate insulating film. ### Claim 11 (depends on 1) The semiconductor device according to claim 1, further comprising: an insulating film formed on the nitride semiconductor layer, wherein a trench is formed in the insulating film and the nitride semiconductor layer, and a lowermost portion of the second gate electrode is formed outside of the trench. ### Claim 12 (depends on 1) The semiconductor device according to claim 1, wherein the nitride semiconductor layer comprises a first nitride semiconductor layer formed on a substrate, and a second nitride semiconductor layer formed on the first nitride semiconductor layer, and wherein a trench is formed in the first and second nitride semiconductor layers and the first gate insulating film contacts the first nitride semiconductor layer in the groove formed in the first nitride semiconductor layer. ### Claim 13 (depends on 12) The semiconductor device according to claim 12, wherein a height of an upper surface of the second gate insulating film in the trench is less than a height of an upper surface of the second nitride semiconductor layer outside of the trench. ### Claim 14 A semiconductor device, comprising: a first nitride semiconductor layer formed above a substrate; a second nitride semiconductor layer formed on the first nitride semiconductor layer; a groove penetrating the second nitride semiconductor layer and reaching the first nitride semiconductor layer; and a gate electrode disposed inside the groove via a gate insulating film, wherein the gate insulating film includes a first gate insulating film provided on the first nitride semiconductor layer and a second gate insulating film provided on the first gate insulating film, the gate electrode includes a first gate electrode formed on a surface of the second gate insulating film and contacting the surface of the second gate insulating film, and a second gate electrode provided on a surface of the first gate electrode and contacting the surface of the first gate electrode, the first gate insulating film is an oxide film containing a first metal or an oxide film containing silicon, the second gate insulating film is an oxide film containing a second metal, an electronegativity of the second metal is smaller than that of the first metal or silicon, the first gate electrode is a nitride film containing a third metal, and the second gate electrode is formed of a fourth metal, wherein the nitride film containing the third metal comprises titanium nitride having a ratio (N/Ti) of nitrogen (N) to titanium (Ti) which is greater than 1. ### Claim 15 A manufacturing method of a semiconductor device, comprising: (a) preparing a nitride semiconductor layer; (b) forming a first gate insulting film on the nitride semiconductor layer, the first gate insulating film being formed of an oxide film containing a first metal or an oxide film containing silicon; (c) forming a second gate insulating film on the first gate insulating film, the second gate insulating film being formed of an oxide film of a second metal; (d) forming a first gate electrode on a surface of the second gate insulating film, the first gate electrode contacting the surface of the second gate insulating film and being formed of a nitride film containing a third metal; and (e) forming a second gate electrode on a surface of the first gate electrode, the second gate electrode contacting the surface of the first gate electrode and being formed of a fourth metal, wherein an electronegativity of the second metal is smaller than that of the first metal or silicon, wherein the nitride film containing the third metal comprises titanium nitride having a ratio (N/Ti) of nitrogen (N) to titanium (Ti) which is greater than 1. ### Claim 16 (depends on 15) The manufacturing method of the semiconductor device according to claim 15, wherein the second gate electrode is formed without exposure to the air in the step (d) to the step (e) after the first gate electrode is formed. ### Claim 17 (depends on 16) The manufacturing method of the semiconductor device according to claim 16, further comprising the step of: (f) performing heat treatment under an inert gas atmosphere after the step (e). ### Claim 18 (depends on 16) The manufacturing method of the semiconductor device according to claim 16, further comprising a step of: (g) processing a stacked film of the first gate electrode and the second gate electrode into a first shape after the step (e). ### Claim 19 (depends on 15) The manufacturing method of the semiconductor device according to claim 15, wherein the first metal is Al. ### Claim 20 (depends on 19) The manufacturing method of the semiconductor device according to claim 19, wherein the second metal is one or more elements selected from a group of Hf, Zr, Ta, Ti, Nb, La, Y and Mg. ### Claim 21 (depends on 15) The manufacturing method of the semiconductor device according to claim 15, wherein the fourth metal is W. ### Claim 22 (depends on 21) The manufacturing method of the semiconductor device according to claim 21, wherein the nitride semiconductor layer is GaN. ### Claim 23 (depends on 15) The manufacturing method of the semiconductor device according to claim 15, wherein the first gate insulating film is formed of an oxide film containing silicon, the second metal is one or more elements selected from a group of Al, Hf, Zr, Ta, Ti, Nb, La, Y and Mg, and the fourth metal is W.