# US 10,374,052 B2 · Reduced capacitance coupling effects in devices

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- Number: US 10,374,052 B2
- Document ID: US10374052B2
- Status: Granted
- Kind: B2
- Application number: 15/730,745
- Filed: 2017-10-12
- Published: 2019-04-18
- Granted: 2019-08-06
- Earliest claimed: 2017-10-12
- Assignees: Globalfoundries Singapore Pte. Ltd.
- Applicants: GLOBALFOUNDRIES Singapore Pte. Ltd.
- Inventors: Shyue Seng Tan; Kiok Boone Elgin Quek; Eng Huat Toh
- Web page: https://patentgrep.com/patent/US10374052B2

## CPC

- H10D 64/671: {the conductor having lateral variation in doping or structure}
- H10D 30/0227: {having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET}
- H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)}
- H10D 30/701: {IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 64/033: {comprising ferroelectric layers}
- H10D 64/118: {Electrodes comprising insulating layers having particular dielectric or electrostatic properties, e.g. having static charges}
- H10D 64/675: {Gate sidewall spacers}
- H10D 64/683: {being parallel to the channel plane}
- H10D 64/689: {having ferroelectric layers}
- H10P 14/69395: {the material containing zirconium, e.g. ZrO2}
- H10P 14/69397: {the material containing two or more metal elements}
- H10P 14/69398: {the material having a perovskite structure, e.g. BaTiO3}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants
- H10W 20/495: {Capacitive arrangements or effects of, or between wiring layers}
- H10D 84/0147: {Manufacturing their gate sidewall spacers}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10W 20/098: {by filling between adjacent conductive parts}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device with reduce capacitance coupling effect which can reduce the overall parasitic capacitances is disclosed. The semiconductor device includes a gate sidewall spacer with a negative capacitance dielectric layer with and without a dielectric layer. The semiconductor device may also include a plurality of interlevel dielectric (ILD) with a layer of negative capacitance dielectric layer followed by a dielectric layer disposed in-between metal lines in any ILD and combinations. The negative capacitance dielectric layer includes a ferroelectric material which has calculated and selected thicknesses with desired negative capacitance to provide optimal total overlap capacitance in the circuit component which aims to reduce the overall capacitance coupling effect.

## Claims

### Claim 1

A semiconductor device comprising:
a substrate having a device region;
a transistor gate having first and second gate sidewalls, the transistor gate disposed on the substrate in the device region, and the transistor gate including a gate dielectric layer and a gate electrode over the gate dielectric layer;
first and second gate sidewall spacers respectively disposed on the first and second gate sidewalls, the first gate sidewall spacer including a first ferroelectric spacer and a first dielectric spacer, the second gate sidewall spacer including a second ferroelectric spacer and a second dielectric spacer, and the first and second ferroelectric spacers each extending from a top of the transistor gate to a bottom of the transistor gate; and
first and second source/drain regions respectively disposed adjacent to the first and second gate sidewalls of the transistor gate,
wherein the first and second ferroelectric spacers comprise first and second L-shaped ferroelectric spacers that respectively line the first and second gate sidewalls and a portion of the substrate adjacent to the first and second gate sidewalls, and the first and second dielectric spacers are respectively disposed on the first and second L-shaped ferroelectric spacers.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the transistor gate comprises a total overlap parasitic capacitance Cov determined by a sum of parasitic capacitances comprising at least a capacitance of the gate dielectric layer (C1), C1 is a positive capacitance value, and a capacitance of the first gate sidewall spacer (C2), and C2 is a negative capacitance value that is substantially equal to the positive capacitance value of C1.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein each of the first and second ferroelectric spacers has a predetermined negative capacitance value relating to a width dimension of the first and second ferroelectric spacers.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein a source/drain region is disposed adjacent to the first gate sidewall of the transistor gate, and further comprising:
a contact coupled with the source/drain region and the gate electrode,
wherein the transistor gate comprises a total overlap parasitic capacitance Cov determined by a sum of parasitic capacitances comprising:
a capacitance of a gate dielectric layer (C1) of the transistor gate, wherein C1 comprises a positive gate dielectric capacitance value;
a capacitance of the first dielectric spacer (C21), wherein C21 comprises a positive first dielectric spacer capacitance value;
a capacitance of the first ferroelectric spacer (C22), wherein C22 comprises a negative first ferroelectric spacer capacitance value;
a capacitance of the contact and the gate electrode (C3); and
wherein Cov>0.

### Claim 5 (depends on 1)

The semiconductor device of claim 1 comprising:
a device well disposed in the device region,
wherein the device region corresponds to a low voltage device region.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein the first and second source/drain regions comprise first polarity type dopants, and the device well comprises second polarity type dopants opposite to the first polarity type.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein a source/drain region is disposed adjacent to the first gate sidewall of the transistor gate, and further comprising:
a contact coupled with the source/drain region,
wherein the transistor gate comprises a total overlap parasitic capacitance Cov determined by a sum of parasitic capacitances comprising:
a capacitance of the gate dielectric layer (C1), wherein C1 comprises a positive capacitance value;
a capacitance of the first gate sidewall spacer (C2), wherein C2 comprises a negative capacitance value;
a capacitance of the contact and the gate electrode (C3); and
wherein Cov>0.

### Claim 8

A semiconductor device comprising:
a substrate having a device region;
a transistor gate having first and second gate sidewalls, the transistor gate disposed on the substrate in the device region, and the transistor gate including a gate dielectric layer and a gate electrode over the gate dielectric layer;
first and second gate sidewall spacers respectively disposed on the first and second gate sidewalls, the first gate sidewall spacer including a first ferroelectric spacer and a first dielectric spacer, the first dielectric spacer disposed on the first gate sidewall, the second gate sidewall spacer including a second ferroelectric spacer and a second dielectric spacer, the second dielectric spacer disposed on the second gate sidewall, and the first and second ferroelectric spacers each extending from a top of the transistor gate to a bottom of the transistor gate; and
first and second source/drain regions respectively disposed adjacent to the first and second gate sidewalls of the transistor gate,
wherein the first and second dielectric spacers respectively line the first and second gate sidewalls, and the first and second ferroelectric spacers are respectively disposed on the first and second dielectric spacers.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, further comprising:
a contact coupled with the first source/drain region,
wherein the transistor gate comprises a total overlap parasitic capacitance Cov determined by a sum of parasitic capacitances comprising:
a capacitance of the gate dielectric (C1), wherein C1 comprises a positive capacitance value;
a capacitance of the first gate sidewall spacer (C2), wherein C2 comprises a negative capacitance value;
a capacitance of the contact and the gate electrode (C3); and
wherein Cov>0.

### Claim 10 (depends on 8)

The semiconductor device of claim 8, wherein the transistor gate comprises a total overlap parasitic capacitance Cov determined by a sum of parasitic capacitances comprising at least a capacitance of the gate dielectric layer (C1), C1 is a positive capacitance value, and a capacitance of the first gate sidewall spacer (C2), and C2 is a negative capacitance value that is substantially equal to the positive capacitance value of C1.

### Claim 11 (depends on 8)

The semiconductor device of claim 8, wherein each of the first and second ferroelectric spacers has a predetermined negative capacitance value relating to a width dimension of the first and second ferroelectric spacers.

### Claim 12 (depends on 8)

The semiconductor device of claim 8, further comprising:
a contact coupled with the first source/drain region,
wherein the transistor gate comprises a total overlap parasitic capacitance Cov determined by a sum of parasitic capacitances comprising:
a capacitance of a gate dielectric layer (C1) of the transistor gate, wherein C1 comprises a positive gate dielectric capacitance value;
a capacitance of the first dielectric spacer (C21), wherein C21 comprises a positive first dielectric spacer capacitance value;
a capacitance of the first ferroelectric spacer (C22), wherein C22 comprises a negative first ferroelectric spacer capacitance value;
a capacitance of the contact (C3) and the gate electrode; and
wherein Cov>0.

### Claim 13 (depends on 8)

The semiconductor device of claim 8 comprising:
a device well disposed in the device region,
wherein the device region corresponds to a low voltage device region.

### Claim 14 (depends on 13)

The semiconductor device of claim 13, wherein the first and second source/drain regions comprise first polarity type dopants, and the device well comprises second polarity type dopants opposite to the first polarity type.