# US 10,374,049 B2 · Heat management in a multi-finger FET

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,374,049 B2
- Document ID: US10374049B2
- Status: Granted
- Kind: B2
- Application number: 15/266,299
- Filed: 2016-09-15
- Published: 2018-03-15
- Granted: 2019-08-06
- Earliest claimed: 2016-09-15
- Assignees: Analog Devices, Inc.
- Applicants: Analog Devices, Inc.
- Inventors: Robert R. Norton
- Web page: https://patentgrep.com/patent/US10374049B2

## CPC

- H10D 64/519: {characterised by their top-view geometrical layouts}
- H10D 30/65: Lateral DMOS [LDMOS] FETs
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H10D 64/257: {for lateral devices wherein the source or drain electrodes are characterised by top-view geometrical layouts, e.g. interdigitated, semi-circular, annular or L-shaped electrodes (source or drain electrodes of TFTs H10D30/673)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

The present disclosure addresses thermal issues in a multi gate finger field-effect transistor (FET) by providing a multi-gate finger FET arrangement where the respective distances between the multiple gate fingers are modulated along the device, such that the distances between the gate fingers in or towards the middle of the device are greater than the distances between the gate fingers at the or towards the edge of the device. By providing the greater distances between gate fingers located in or towards the middle of the device then improved thermal management properties are obtained, and the device as a whole is maintained cooler than would otherwise be the case, with associated improvements in device lifetimes.

## Claims

### Claim 1

A transistor device configured for thermal energy management, the transistor device comprising a plurality of active regions formed within a semiconductor substrate, the active regions being respectively separated by other regions having electrode fingers formed thereon, the electrode fingers being electrically connected to a common gate terminal and comprising conductive elements separated one from another by respective inter-electrode distances, at least three inter-electrode distances increasing from each of two opposing edges of the transistor device towards a middle of the transistor device.

### Claim 2 (depends on 1)

The transistor device according to claim 1, wherein the transistor is a multi-gate finger field-effect transistor (FET), and the active regions are source and drain regions alternating across the transistor device, the source and drain regions being separated one from the other by respective channel regions, the electrode fingers being elongate gate electrodes.

### Claim 3 (depends on 1)

The transistor device according to claim 1, wherein the conductive elements are elongate and extend substantially parallel to one another.

### Claim 4 (depends on 3)

The transistor device according to claim 3, wherein the active regions extend in a linear array next to one another from one side of the transistor device to the other side of the transistor device and separated by the other regions, the elongate conductive elements extending substantially orthogonally to a direction of extension of the linear array.

### Claim 5 (depends on 1)

The transistor device according to claim 1, wherein the inter-electrode distances increase by a fixed amount from one distance to the next towards the middle of the device.

### Claim 6 (depends on 1)

The transistor device according to claim 1, wherein the inter-electrode distances increase by a relative fractional amount from one distance to the next towards the middle of the device.

### Claim 7 (depends on 1)

The transistor device according to claim 1, wherein each of the inter-electrode distances is arranged to be less than a maximum permitted inter electrode distance.

### Claim 8

A multi-gate finger field-effect transistor (FET) configured for power amplification applications that raise thermal energy levels within the FET during operation, the multi-gate finger FET comprising:
an array of alternating source and drain regions separated by respective channel regions; and
conductive gate fingers extending over the channel regions, the conductive gate fingers being electrically connected to a common gate terminal,
wherein at least three distances between adjacent gate fingers are modulated according to a monotonic function from each of two opposing edges of the array towards a middle of the array.

### Claim 9 (depends on 8)

The multi-gate finger FET according to claim 8, wherein the monotonic function is such that the respective distances between adjacent fingers from the edges of the array towards the middle of the array increase by a fixed amount.

### Claim 10 (depends on 8)

The multi-gate finger FET according to claim 8, wherein the monotonic function is such that the respective distances between adjacent fingers from the edges of the array towards the middle of the array increase by a relative amount.

### Claim 11 (depends on 10)

The multi-gate finger FET according to claim 10, wherein the monotonic function is such that a second distance between a pair of gate fingers is greater than a first distance between another pair of gate fingers by a fraction of the first distance.

### Claim 12 (depends on 8)

The multi-gate finger FET according to claim 8, wherein the respective distances between adjacent gate fingers are symmetrical about the middle of the array.

### Claim 13 (depends on 8)

The multi-gate finger FET according to claim 8, wherein the respective distances between adjacent fingers are modulated according to the monotonic function without exceeding a maximum allowable distance between gate fingers.

### Claim 14 (depends on 8)

The multi-gate finger FET according to claim 8, wherein respective widths of the alternating source and drain regions are adapted to give the respective distances between the gate fingers, the respective channel widths being substantially identical.

### Claim 15

A multi-gate transistor having multiple gate electrodes formed over respective channel regions, the multiple gate electrodes being electrically connected to a common gate terminal and separated from each other by inter-gate distances, wherein the inter-gate distances increase from opposing edges of the multi-gate transistor towards a middle of the multi-gate transistor, and wherein at least first, second and third consecutive inter-gate distances between at least four of the multiple gate electrodes increase from distance to distance such that the third inter-gate distance is larger than the second inter-gate distance, and the second inter-gate distance is larger than the first inter-gate distance.

### Claim 16 (depends on 15)

The multi-gate transistor according to claim 15, wherein the three consecutive inter-gate distances increase by a fixed amount from distance to distance.

### Claim 17 (depends on 16)

The multi-gate transistor according to claim 16, wherein the fixed amount is within the range 10% to 40% of the first inter-gate distance.

### Claim 18 (depends on 15)

The multi-gate transistor according to claim 15, wherein the three consecutive inter-gate distances increase by a predetermined percentage amount of the previous inter-gate distance, whereby the second inter-gate distance is a fraction of the first inter-gate distance larger than the first inter-gate distance, and the third inter-gate distance is a fraction of the second inter-gate distance larger than the second inter-gate distance.

### Claim 19 (depends on 18)

The multi-gate transistor according to claim 18, wherein the predetermined percentage amount is within the range 10% to 40%.

### Claim 20 (depends on 15)

The multi-gate transistor according to claim 15, wherein the multiple gate electrodes comprise electrically common elongate fingers extending over the channel regions substantially parallel to each other.

### Claim 21

A transistor device configured to manage heat dissipation thereacross, the transistor device comprising:
a plurality of heat-generating channel regions and a plurality of active regions alternatingly arranged in a semiconductor substrate such that each of the heat-generating channel regions is formed between two adjacent active regions, wherein volumes of the semiconductor substrate available for dissipation of heat from at least three of the heat-generating channel regions decrease from a center of the transistor device towards each of opposing edges of the transistor device; and
a gate electrode configured for adjusting a rate of heat dissipation across the transistor device.

### Claim 22 (depends on 21)

The transistor device of claim 21, wherein the at least three of the heat-generating channel regions with decreasing volumes comprise three consecutive heat-generating channel regions.

### Claim 23 (depends on 21)

The transistor device of claim 21, wherein the gate electrode comprises gate electrode fingers over each of the volumes of the semiconductor substrate, wherein distances between adjacent ones of the gate electrode fingers decrease from the center of the transistor device towards the each of the opposing edges of the transistor device.