# US 10,374,048 B2 · Asymmetric high-k dielectric for reducing gate induced drain leakage

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- Number: US 10,374,048 B2
- Document ID: US10374048B2
- Status: Granted
- Kind: B2
- Application number: 15/813,314
- Filed: 2017-11-15
- Published: 2018-03-15
- Granted: 2019-08-06
- Earliest claimed: 2014-11-25
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Anthony I. Chou; Arvind Kumar; Chung-Hsun Lin; Shreesh Narasimha; Claude Ortolland; Jonathan T. Shaw
- Web page: https://patentgrep.com/patent/US10374048B2

## CPC

- H10D 64/516: {the thicknesses being non-uniform}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6217: {having non-uniform gate electrodes, e.g. gate conductors having varying doping}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 64/01: Manufacture or treatment
- H10D 64/01332: {Making the insulator}
- H10D 64/01338: {with a treatment, e.g. annealing, after the formation of the conductor}
- H10D 64/0134: {with a treatment, e.g. annealing, after the formation of the insulator and before the formation of the conductor}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 64/512: {Disposition of the gate electrodes, e.g. buried gates}
- H10D 64/681: {having a compositional variation, e.g. multilayered}
- H10D 64/683: {being parallel to the channel plane}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D 84/0144: {Manufacturing their gate insulating layers}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 86/011: {comprising FinFETs}
- H10P 14/40: of conductive or resistive materials
- H10P 14/6304: {Formation by oxidation, e.g. oxidation of the substrate}
- H10P 14/6316: {Formation by nitridation, e.g. nitridation of the substrate}
- H10P 14/6322: {Formation by thermal treatments (formation by plasma treatment H10P14/6319)}
- H10P 14/6519: {the substance being oxygen}
- H10P 14/6526: {introduced into an oxide material, e.g. changing SiO to SiON}
- H10P 14/69392: {the material containing hafnium, e.g. HfO2}
- H10P 30/20: into semiconductor materials, e.g. for doping
- H10P 30/22: using masks
- H10P 30/221: {characterised by the angle between the ion beam and the mask}
- H10P 30/222: {characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221)}
- H10P 30/40: into insulating materials
- H10P 50/694: {characterised by their behaviour during the process, e.g. soluble masks or redeposited masks}
- H10P 95/90: Thermal treatments, e.g. annealing or sintering
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.

## Claims

### Claim 1

A method, comprising:
performing a damaging implant process on a sidewall on a source side of a gate structure; and
performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure adjacent to a drain region, while inhibiting oxide growth on the sidewall on the source side of the gate structure adjacent to a source region,
wherein the gate structure is a finFET gate.

### Claim 2 (depends on 1)

The method of claim 1, wherein the damaging implant process comprises deposition of a masking material overlapping the source side of the gate structure.

### Claim 3 (depends on 2)

The method of claim 2, wherein the masking material is a nitrogen material.

### Claim 4 (depends on 1)

The method of claim 1, wherein oxygen is prevented from channeling into a substrate via a high-k material on the sidewall on the source side.

### Claim 5 (depends on 4)

The method of claim 4, wherein the high-k material on the sidewall is composed of HfO2.

### Claim 6 (depends on 1)

The method of claim 1, wherein the oxygen annealing process is a low temperature oxygen anneal.

### Claim 7 (depends on 6)

The method of claim 6, wherein the low temperature oxygen anneal is at 500° C. for about 30 minutes.

### Claim 8 (depends on 7)

The method of claim 7, wherein a thickness of the oxide region is controlled by adjusting the low temperature oxygen anneal.

### Claim 9 (depends on 8)

The method of claim 8, wherein the thickness of the oxide region increases from about 1.5 nm to about 1.8 nm.

### Claim 10

A method, comprising:
performing a damaging implant process on a sidewall on a source side of a gate structure; and
performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure adjacent to a drain region, while inhibiting oxide growth on the sidewall on the source side of the gate structure adjacent to a source region,
wherein the damaging implant process is an asymmetric nitrogen implant process.