# US 10,374,047 B2 · Semiconductor device and manufacturing method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,374,047 B2 - Document ID: US10374047B2 - Status: Granted - Kind: B2 - Application number: 15/889,507 - Filed: 2018-02-06 - Published: 2018-08-09 - Granted: 2019-08-06 - Earliest claimed: 2017-02-07 - Assignees: Rohm Co., Ltd. - Applicants: Rohm Co., Ltd. - Inventors: Hajime Okuda; Adrian Joita - Web page: https://patentgrep.com/patent/US10374047B2 ## CPC - H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates} - H10D 12/038: {having a recessed gate, e.g. trench-gate IGBTs} - H10D 12/481: {having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs} - H10D 30/0223: {having source and drain regions or source and drain extensions self-aligned to sides of the gate} - H10D 30/0285: {using formation of insulating sidewall spacers} - H10D 30/0289: {using recessing of the gate electrodes, e.g. to form trench gate electrodes} - H10D 30/0297: {using recessing of the gate electrodes, e.g. to form trench gate electrodes} - H10D 30/66: Vertical DMOS [VDMOS] FETs - H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors} - H10D 62/155: {Shapes (cell layout of DMOS H10D62/127)} - H10D 64/117: {Recessed field plates, e.g. trench field plates or buried field plates} - H10D 64/518: {characterised by their lengths or sectional shapes} - H10D 84/85: Complementary IGFETs, e.g. CMOS - H10D 84/856: {the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS} - H10P 30/222: {characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221)} - H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence) - H10D 62/141: {Anode or cathode regions of thyristors; Collector or emitter regions of gated bipolar-mode devices, e.g. of IGBTs} - H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor device includes a semiconductor layer of a first conductivity type having a main surface at which a trench is formed, a gate insulating layer formed along a side wall of the trench, a gate electrode embedded in the trench with the gate insulating layer interposed therebetween and having an upper surface located below the main surface of the semiconductor layer, a second conductivity type region formed in a surface layer portion of the main surface of the semiconductor layer and facing the gate electrode with the gate insulating layer interposed therebetween, a first conductivity type region formed in a surface layer portion of the second conductivity type region and facing the gate electrode with the gate insulating layer interposed therebetween, and a side wall insulating layer covering the side wall of the trench in a recessed portion defined by the side wall of the trench and the upper surface of the gate electrode. ## Claims ### Claim 1 A semiconductor device comprising: a semiconductor layer of a first conductivity type having a main surface at which a trench is formed; a gate insulating layer formed along a side wall of the trench; a gate electrode embedded in the trench with the gate insulating layer interposed therebetween and having an upper surface located below the main surface of the semiconductor layer; a second conductivity type region formed in a surface layer portion of the main surface of the semiconductor layer and facing the gate electrode with the gate insulating layer interposed therebetween; a first conductivity type region formed in a surface layer portion of the second conductivity type region and facing the gate electrode with the gate insulating layer interposed therebetween; and a side wall insulating layer covering the side wall of the trench in a recessed portion defined by the side wall of the trench and the upper surface of the gate electrode. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein the side wall insulating layer covers the side wall of the trench with the gate insulating layer interposed therebetween in the recessed portion. ### Claim 3 (depends on 1) The semiconductor device according to claim 1, wherein the side wall insulating layer covers the side wall of the trench and the upper surface of the gate electrode in the recessed portion. ### Claim 4 (depends on 1) The semiconductor device according to claim 1, wherein the side wall insulating layer is formed along a corner portion formed by the side wall of the trench and the upper surface of the gate electrode. ### Claim 5 (depends on 1) The semiconductor device according to claim 1, wherein the side wall insulating layer has a curved surface protruding in a curved shape from the side wall of the trench toward the upper surface of the gate electrode. ### Claim 6 (depends on 1) The semiconductor device according to claim 1, wherein the side wall insulating layer includes a same insulating material as an insulating material of the gate insulating layer. ### Claim 7 (depends on 1) The semiconductor device according to claim 1, wherein the side wall insulating layer includes an insulating material different from insulating material of the gate insulating layer. ### Claim 8 (depends on 1) The semiconductor device according to claim 1 further 20 comprising: a lower insulating layer formed along an inside wall of the trench in a region of the trench below the gate electrode; an embedded electrode embedded in the trench with the lower insulating layer interposed therebetween in a region of the trench below the gate electrode; and an intermediate insulating layer formed in a region between the gate electrode and the embedded electrode. ### Claim 9 A manufacturing method of a semiconductor device comprising steps of: forming a trench at a main surface of a semiconductor wafer of a first conductivity type; forming a gate insulating layer along a side wall of the trench; embedding a gate electrode into the trench such that an upper surface of the gate electrode is to be located below the main surface of the semiconductor wafer; forming a second conductivity type region along the side wall of the trench by introducing a second conductivity type impurity into the surface layer portion of the main surface of the semiconductor wafer in a side of the trench; forming a side wall insulating layer covering the side wall of the trench in a recessed portion defined by the side wall of the trench and the upper surface of the gate electrode; and forming a first conductivity type region along the side wall of the trench in a surface layer portion of the second conductivity type region by introducing a first conductivity type impurity into the surface layer portion of the second conductivity type region via the side wall insulating layer. ### Claim 10 (depends on 9) The manufacturing method of the semiconductor device according to claim 9, wherein the step of forming the first conductivity type region includes a step of introducing the first conductivity type impurity into the surface layer portion of the second conductivity type region via the side wall insulating layer by an oblique ion implantation method. ### Claim 11 (depends on 9) The manufacturing method of the semiconductor device according to claim 9, wherein the step of forming the second conductivity type region includes a step of introducing the second conductivity type impurity into the surface layer portion of the main surface of the semiconductor wafer from the side wall of the trench by an oblique ion implantation method. ### Claim 12 (depends on 9) The manufacturing method of the semiconductor device according to claim 9, wherein the step of forming of the side wall insulating layer includes a step of forming an insulating layer along an inner wall of the recessed portion defined by the side wall of the trench and the upper surface of the gate electrode in addition to the main surface of the semiconductor wafer, and a step of selectively removing an unnecessary portion of the insulating layer such that a part covering the side wall of the trench in the insulating layer remains. ### Claim 13 (depends on 9) The manufacturing method of the semiconductor device according to claim 9, wherein the step of forming of the gate electrode includes a step of forming a conductive layer embedding the trench and covering the main surface of the semiconductor wafer, and a step of selectively removing an unnecessary portion of the conductive layer until an upper surface of the conductive layer reaches below the main surface of the semiconductor wafer in the trench. ### Claim 14 A semiconductor wafer structure comprising: a semiconductor wafer of a first conductivity type set a first device formation region in which a first semiconductor device is to be formed and a second device formation region in which a second semiconductor device is to be formed, and having a main surface at which trenches are formed in each of the first device formation region and the second device formation region; wherein the first device formation region and the second device formation region each include a gate insulating layer formed along a side wall of the trench, a gate electrode embedded in the trench with the gate insulating layer interposed therebetween and having an upper surface located below the main surface of the semiconductor wafer, a second conductivity type region formed in a surface layer portion of the main surface of the semiconductor layer and facing the gate electrode with the gate insulating layer interposed therebetween, and a first conductivity type region formed in a surface layer portion of the second conductivity type region and facing the gate electrode with the gate insulating layer interposed therebetween, wherein the upper surface of the gate electrode formed in the second device formation region is located below the upper surface of the gate electrode formed in the first device formation region, and the second device formation region includes a side wall insulating layer covering the side wall of the trench in a recessed portion defined by the side wall of the trench and the upper surface of the gate electrode. ### Claim 15 (depends on 14) The semiconductor wafer structure according to claim 14, wherein the first device formation region includes the side wall insulating layer in addition to the second device formation region. ### Claim 16 (depends on 14) The semiconductor wafer structure according to claim 14, wherein a lower portion of the second conductivity type region formed in the second device formation region is located below a lower portion of the second conductivity type region formed in the first device formation region. ### Claim 17 (depends on 14) The semiconductor wafer structure according to claim 14, wherein the first device formation region is set at a center portion of the main surface of the semiconductor wafer, and the second device formation region is set at a side of a peripheral portion of the main surface of the semiconductor wafer with respect to the first device formation region. ### Claim 18 (depends on 14) The semiconductor wafer structure according to claim 14, wherein the second conductivity type region includes a channel formed in a region in which the second conductivity type region faces the gate electrode with the insulating layer interposed therebetween, an absolute value of a difference between a first channel length along a thickness direction of the semiconductor wafer in the channel formed in a first device formation region and a second channel length along the thickness direction of the semiconductor wafer in the channel formed in a second device formation region is equal to or greater than 0% and equal to or less than 10% of an average value obtained from the first channel length and the second channel length. ### Claim 19 (depends on 14) The semiconductor wafer structure according to claim 14, wherein the second conductivity type region includes a channel formed in a region in which the second conductivity type region faces the gate electrode with the insulating layer interposed therebetween, an absolute value of a difference between a first channel length along the thickness direction of the semiconductor wafer in the channel formed in a first device formation region and a second channel length along a thickness direction of the semiconductor wafer in the channel formed in a second device formation region is equal to or greater than 0 μm and equal to or less than 0.1 μm.