# US 10,374,046 B2 · Structure for reduced source and drain contact to gate stack capacitance

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- Number: US 10,374,046 B2
- Document ID: US10374046B2
- Status: Granted
- Kind: B2
- Application number: 15/396,796
- Filed: 2017-01-02
- Published: 2017-06-22
- Granted: 2019-08-06
- Earliest claimed: 2015-12-17
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Carl J Radens; Richard Q Williams
- Web page: https://patentgrep.com/patent/US10374046B2

## CPC

- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 30/6729: {characterised by the electrodes}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6737: {characterised by the electrode materials}
- H10D 30/6743: {Silicon}
- H10D 30/6744: {Monocrystalline silicon}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/258: {characterised by the relative positions of the source or drain electrodes with respect to the gate electrode}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10P 50/642: {Chemical etching}
- H10P 52/402: {of semiconductor materials}
- H10P 72/74: {using temporarily an auxiliary support}
- H10P 76/204: {of organic photoresist masks}
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/0245: {comprising use of blind vias during the manufacture}
- H10W 20/0249: {wherein the through-semiconductor via protrudes from backsides of the chips, wafers or substrates during the manufacture}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/0698: {Local interconnections}
- H10W 20/076: {in via holes or trenches}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/218: {in silicon-on-insulator [SOI] wafers}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/43: Layouts of interconnections
- H10W 20/4405: {the principal metal being aluminium}
- H10W 20/4421: {the principal metal being copper}
- H10W 20/4424: {Copper alloys}
- H10W 20/4441: {the principal metal being a refractory metal}
- H10W 20/481: {on the rear surfaces of the wafers or substrates}
- H10P 72/7412: {the auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support}
- H10P 72/7416: {used during dicing or grinding}
- H10P 72/7422: {used to protect an active side of a device or wafer}
- H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A structure of a semiconductor device is described. In one aspect of the invention, a FinFET semiconductor device includes a FinFET transistor which includes a source region and a drain region disposed in a fin on a first surface of a substrate. A gate structure is disposed over a central portion of the fin. A wiring layer of conductive material is disposed over a second surface of the substrate which is opposite to the first surface of the substrate. A set of contact studs include a first contact stud which extends completely through the height of the fin in the source region and the substrate to the wiring layer. The set of contact studs also includes a second contact stud which extends completely through the height of the fin in the drain region and the substrate to the wiring layer. In other aspects of the invention, the device is a Nanosheet device or an inverter.

## Claims

### Claim 1

A FinFET semiconductor device comprising:
a FinFET transistor including a source region and a drain region disposed in a fin on a first surface of a substrate, wherein the transistor further includes a gate structure disposed over a central portion of the fin;
a wiring layer of conductive material disposed over a second surface of the substrate, the second surface of the substrate opposite to the first surface of the substrate; and
a set of contact studs including a first contact stud extending completely through a height of the fin in the source region and extending through the substrate to a first respective portion of the wiring layer and a second contact stud extending completely through a height of the fin in the drain region and extending through the substrate to a second respective portion of the wiring layer, wherein the contact studs are comprised of a metal.

### Claim 2 (depends on 1)

The device as recited in claim 1, further comprising crystalline silicon grown over the source and drain regions of the fin.

### Claim 3 (depends on 2)

The device as recited in claim 2, wherein the first contact stud and the second contact stud respectively extend through the crystalline silicon grown over the source and drain regions of the fin.

### Claim 4 (depends on 1)

The device as recited in claim 1, wherein the substrate comprises a layer of buried oxide dielectric material disposed between the transistor and a second layer of the substrate layer.

### Claim 5 (depends on 1)

The device as recited in claim 1, wherein the first contact stud electrically connects the source region in the fin to the first respective portion of the wiring layer on the second surface of the substrate and the second contact stud electrically connects the drain region in the fin to the second respective portion of the wiring layer.

### Claim 6 (depends on 1)

The device as recited in claim 1, wherein the set of contact studs are coated by an isolation layer in a semiconductor substrate layer and are free of the isolation layer in the source region and the drain region.

### Claim 7 (depends on 1)

The device as recited in claim 1, wherein a first end of each of the first and second contact studs terminates at a top surface of the fin.