# US 10,374,042 B2 · Semiconductor device including epitaxially formed buried channel region

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- Number: US 10,374,042 B2
- Document ID: US10374042B2
- Status: Granted
- Kind: B2
- Application number: 14/840,279
- Filed: 2015-08-31
- Published: 2017-03-02
- Granted: 2019-08-06
- Earliest claimed: 2015-08-31
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Jie Deng; Pranita Kerber; Qiqing C. Ouyang; Alexander Reznicek
- Web page: https://patentgrep.com/patent/US10374042B2

## CPC

- H10D 30/751: {having composition variations in the channel regions}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/235: {of IGFETs (IGFETs having buried channels H10D30/637)}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device includes at least one semiconductor fin on an upper surface of a substrate. The at least one semiconductor fin includes a channel region interposed between opposing source/drain regions. A gate stack is on the upper surface of the substrate and wraps around sidewalls and an upper surface of only the channel region. The channel region is a dual channel region including a buried channel portion and a surface channel portion that completely surrounds the buried channel.

## Claims

### Claim 1

A semiconductor device, comprising:
at least one semiconductor fin on an upper surface of a substrate that includes a buried insulator layer, the at least one semiconductor fin including a fin body composed entirely of a first semiconductor material that extends from the upper surface of the buried insulator layer to an upper surface of the at least one semiconductor fin, and including a dual-channel region interposed between opposing source/drain regions; and
a gate stack on the upper surface of the substrate and wrapping around sidewalls and an upper surface of only the channel region, the gate stack including a first gate spacer interposed between a first source/drain region of the opposing source/drain regions and the dual-channel region, and a second gate spacer interposed between a second source/drain region of the opposing source/drain regions,
wherein the dual channel region comprises a portion of the fin body to define a buried channel portion and a surface channel portion on the buried channel portion that completely surrounds sidewalls and the upper surface of the buried channel portion, and
wherein the surface channel portion does not extend beyond inner sidewalls of the first and second gate spacers.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the surface channel portion comprises a heterojunction semiconductor material.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein the heterojunction semiconductor material includes a doped impurity.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, wherein the heterojunction semiconductor material is (SiGe) doped with boron (B) to define a NMOS transistor, or the heterojunction semiconductor material is SiGe doped with phosphorus (P) to define a PMOS transistor.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein the buried channel portion is formed from silicon (Si).

### Claim 6 (depends on 2)

The semiconductor device of claim 2, wherein the surface channel portion is configured to provide a first carrier density and the buried channel portion is configured to provide a second carrier density that is greater than the first carrier density by at least an order of magnitude in the on-state.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, wherein the surface channel region is configured to reduce carrier trapping in the gate stack.

### Claim 8 (depends on 2)

The semiconductor device of claim 2, wherein the surface channel portion directly contacts the buried channel portion and directly contacts the gate stack.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein the buried channel portion is separated from the gate stack by a distance equal to the thickness of the surface channel portion.