# US 10,374,041 B2 · Field effect transistor with controllable resistance

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- Number: US 10,374,041 B2
- Document ID: US10374041B2
- Status: Granted
- Kind: B2
- Application number: 15/850,098
- Filed: 2017-12-21
- Published: 2019-06-27
- Granted: 2019-08-06
- Earliest claimed: 2017-12-21
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Yulong Li; Paul M. Solomon; Siyuranga Koswatta
- Web page: https://patentgrep.com/patent/US10374041B2

## CPC

- H10D 62/307: {the doping variations being parallel to the channel lengths}
- H10B 12/30: {DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells}
- H10B 41/30: characterised by the memory core region
- H10B 51/30: characterised by the memory core region
- H10B 63/00: Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10D 12/211: {Gated diodes}
- H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT}
- H10D 30/0221: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]}
- H10D 30/0318: {of vertical TFTs}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 30/6728: {Vertical TFTs}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6741: {Group IV materials, e.g. germanium or silicon carbide (TFTs having oxide semiconductors H10D30/6755)}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 30/681: {having only two programming levels (Floating gate IGFETs programmable by two single electrons H10D30/688)}
- H10D 30/6891: {characterised by the shapes, relative sizes or dispositions of the floating gate electrode}
- H10D 30/751: {having composition variations in the channel regions}
- H10D 30/801: {FETs having heterojunction gate electrodes}
- H10D 48/366: {Multistable devices; Devices having two or more distinct operating states}
- H10D 48/383: {Quantum effect devices, e.g. of devices using quantum reflection, diffraction or interference effects}
- H10D 62/114: {PN junction isolations}
- H10D 62/17: Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 62/824: comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
- H10D 64/033: {comprising ferroelectric layers}
- H10D 64/035: {comprising conductor-insulator-conductor-insulator-semiconductor structures}
- H10D 64/27: Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D 64/671: {the conductor having lateral variation in doping or structure}
- H10D 64/689: {having ferroelectric layers}
- H10D 30/0411: {of FETs having floating gates}
- H10D 30/0415: {of FETs having ferroelectric gate insulators}
- H10D 30/68: Floating-gate IGFETs
- H10D 30/701: {IGFETs having ferroelectric gate insulators, e.g. ferroelectric FETs}
- H10D 62/121: {oriented parallel to substrates}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

Embodiments of the invention are directed to a method and resulting structures for a semiconductor device having a controllable resistance. An example method for forming a semiconductor device includes forming a source terminal and a drain terminal of a field effect transistor (FET) on a substrate. The source terminal and the drain terminal are formed on either sides of a channel region. An energy barrier is formed adjacent to the source terminal and the channel region. A conductive gate is formed over the channel region.

## Claims

### Claim 1

A method for forming a semiconductor device, the method comprising:
forming a source terminal and a drain terminal of a field effect transistor (FET) on a substrate, the source terminal and the drain terminal formed on either side of a channel region by recessing the substrate;
forming an energy barrier adjacent to the source terminal and the channel region by etching the energy barrier in recesses formed by the recessing; and
forming a conductive gate over the channel region.

### Claim 2 (depends on 1)

The method of claim 1, wherein the energy barrier and the channel region are doped using a first dopant, the energy barrier having a higher doping concentration than the channel region.

### Claim 3 (depends on 2)

The method of claim 2, wherein the source terminal and the drain terminal are doped using a second dopant.

### Claim 4 (depends on 1)

The method of claim 1 further comprising forming a sidewall spacer adjacent to the conductive gate, wherein a charge stored on the gate generates a fringing field in the sidewall spacer, which modulates a height of the energy barrier.

### Claim 5 (depends on 1)

The method of claim 1, wherein the energy barrier is formed from a hetero-barrier material.

### Claim 6 (depends on 1)

The method of claim 1 further comprising forming a floating gate in the conductive gate.

### Claim 7 (depends on 1)

The method of claim 1 further comprising forming a layer of a ferroelectric material on a metal layer in the conductive gate.