# US 10,374,040 B1 · Method to form low resistance contact

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- Number: US 10,374,040 B1
- Document ID: US10374040B1
- Status: Granted
- Kind: B1
- Application number: 16/005,832
- Filed: 2018-06-12
- Granted: 2019-08-06
- Earliest claimed: 2018-06-12
- Assignees: Globalfoundries Inc.
- Applicants: Globalfoundries Inc.
- Inventors: Daniel Chanemougame; Lars Liebmann; Ruilong Xie
- Web page: https://patentgrep.com/patent/US10374040B1

## CPC

- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/258: {characterised by the relative positions of the source or drain electrodes with respect to the gate electrode}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/834: {comprising FinFETs}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10W 20/035: {combinations of barrier, adhesion or liner layers, e.g. multi-layered barrier layers}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/076: {in via holes or trenches}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/43: Layouts of interconnections
- H10D 30/0212: {using self-aligned silicidation}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10W 20/083: {the openings being via holes penetrating underlying conductors}
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

In the manufacture of a semiconductor device, electrical interconnects are formed by depositing a dielectric layer over source/drain regions, and forming a continuous trench within the dielectric layer. The trench may traverse plural source/drain regions associated with adjacent devices. The electrical interconnects are thereafter formed by metallizing the trench and patterning the metallization layers to form discrete interconnects over and in electrical contact with respective source/drain regions. The source/drain interconnects exhibit a reentrant profile, which presents a larger contact area to later-formed conductive contacts than a conventional tapered profile, and thus improve manufacturability and yield.

## Claims

### Claim 1

A semiconductor device, comprising:
a source/drain region disposed over a semiconductor material layer;
an interconnect structure disposed over and in electrical contact with the source/drain region, the interconnect structure including a conductive liner disposed over the source/drain region and a conductive fill layer disposed over the conductive liner, wherein the interconnect structure has a reentrant profile in which a horizontal critical dimension in an upper portion of the interconnect structure is smaller than a horizontal critical dimension in a lower portion of the interconnect structure; and
a conductive contact disposed over the interconnect structure and in direct physical contact with at least sidewalls of the interconnect structure.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein at least the conductive fill layer of the interconnect structure has a reentrant profile.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein the conductive liner comprises a metal silicide.

### Claim 4 (depends on 2)

The semiconductor device of claim 2, wherein sidewalls of the conductive fill layer are oriented at an angle of between 90° and 150° with respect to a top surface of the semiconductor material layer external to the conductive fill layer.

### Claim 5 (depends on 2)

The semiconductor device of claim 2, further comprising a dielectric layer disposed directly over sidewalls of the conductive fill layer.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, further comprising a dielectric layer disposed over the interconnect structure.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, further comprising a conductive contact extending through the dielectric layer and in electrical contact with the interconnect structure.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein the conductive contact is in electrical contact with sidewalls of the conductive fill layer.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein the conductive contact is in electrical contact with sidewalls and a top surface of the conductive fill layer.

### Claim 10

A semiconductor device, comprising:
a source/drain region disposed over a semiconductor material layer;
an interconnect structure disposed over and in electrical contact with the source/drain region, the interconnect structure including a conductive liner disposed over the source/drain region and a conductive fill layer disposed over the conductive liner, wherein the interconnect structure has a reentrant profile in which a horizontal critical dimension in an upper portion of the interconnect structure is smaller than a horizontal critical dimension in a lower portion of the interconnect structure by virtue of a width of the conductive fill layer being smaller at an upper portion of the conductive fill layer than the width is at a lower portion of the conductive fill layer; and
a conductive contact in electrical contact with sidewalls and a top surface of the interconnect structure.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, where a portion of an outermost sidewall of the conductive contact extends beyond an outermost sidewall of the interconnect structure and another portion of the outermost sidewall of the conductive contact extends below the top surface of the conductive fill layer to extend along and engage a portion of at least one sidewall of the conductive fill layer.

### Claim 12

A method of forming a semiconductor device, comprising:
forming a semiconductor material layer over a semiconductor substrate, the semiconductor material layer having alternating source/drain and channel regions;
forming a metallization architecture over and extending between plural source/drain regions;
patterning and etching the metallization architecture to form an interconnect structure over at least one source/drain region, including:
forming a conductive liner of the interconnect structure over the at least one source/drain region; and
forming a conductive fill layer of the interconnect structure over the conductive liner and with a reentrant profile in which an external sidewall of the conductive fill layer forms an angle with a horizontal surface external of the conductive fill layer of between 90° and 150°; and
forming a dielectric layer over the interconnect structure;
forming a contact opening from the top of the dielectric layer to expose a portion of the conductive fill layer; and
forming a conductive contact in the opening such that the conductive contact extends from a top surface of the dielectric layer to make direct contact with the exposed portion of the conductive fill layer.

### Claim 13 (depends on 12)

The method of claim 12, wherein the exposed portion includes a top surface of the conductive fill layer of the interconnect structure.

### Claim 14 (depends on 12)

The method of claim 12, wherein the exposed portion includes an external sidewall of the conductive fill layer extending below a top surface of the conductive fill layer.

### Claim 15 (depends on 12)

The method of claim 12, wherein forming the metallization architecture comprises forming a dielectric layer over the source/drain regions and forming an interconnect trench in the dielectric layer.

### Claim 16 (depends on 12)

The method of claim 12, wherein the metallization architecture extends over a shallow trench isolation layer between adjacent source/drain regions.

### Claim 17 (depends on 12)

The method of claim 12, further comprising forming a dielectric layer between the interconnect structures.

### Claim 18 (depends on 12)

The method of claim 12, wherein forming the contact opening includes recessing the conductive fill layer so that the contact opening extends through a portion of the conductive fill layer and the exposed portion includes a horizontal surface extending from an external sidewall of the conductive fill layer below a top surface of the conductive fill layer.