# US 10,374,039 B1 · Enhanced field bipolar resistive RAM integrated with FDSOI technology

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- Number: US 10,374,039 B1
- Document ID: US10374039B1
- Status: Granted
- Kind: B1
- Application number: 15/962,848
- Filed: 2018-04-25
- Granted: 2019-08-06
- Earliest claimed: 2018-04-25
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Pouya Hashemi; Takashi Ando; Alexander Reznicek
- Web page: https://patentgrep.com/patent/US10374039B1

## CPC

- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors}
- H10D 30/0323: {comprising monocrystalline silicon}
- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 30/6744: {Monocrystalline silicon}
- H10D 62/235: {of IGFETs (IGFETs having buried channels H10D30/637)}
- H10D 86/01: Manufacture or treatment
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10N 70/021: {Formation of switching materials, e.g. deposition of layers}
- H10N 70/066: {by filling of openings, e.g. damascene method}
- H10N 70/24: {based on migration or redistribution of ionic species, e.g. anions, vacancies}
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- H10N 70/8418: {adapted for focusing electric field or current, e.g. tip-shaped}
- H10N 70/8833: {Binary metal oxides, e.g. TaOx}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

A resistive random access memory stack is formed on a surface of a faceted drain-side structure that is present on one side of a functional gate structure. The functional gate structure and the faceted drain-side structure are located on a topmost surface of a fully depleted semiconductor channel material layer. In some embodiments, the resistive random access memory stack includes a bottom electrode, a resistive switching layer and a top electrode. In other embodiments, the resistive random access memory stack includes a resistive switching layer and a top electrode. In such an embodiment, a drain-side metal semiconductor alloy of the faceted drain-side structure is used as the bottom electrode of the resistive random access memory device.

## Claims

### Claim 1

A semiconductor structure comprising:
a functional gate structure located on a topmost surface of a fully depleted semiconductor channel material layer;
a faceted drain-side structure located on the topmost surface of the fully depleted semiconductor channel material layer and present on a first side of the functional gate structure;
a faceted source-side structure located on the topmost surface of the fully depleted semiconductor channel material layer and present on a second side of the functional gate structure that is opposite the first side; and
a resistive random access memory stack located on a surface of the faceted drain-side structure.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein the resistive random access memory stack includes a bottom electrode, a resistive switching layer and a top electrode.

### Claim 3 (depends on 2)

The semiconductor structure of claim 2, wherein the top electrode has a topmost surface that is coplanar with a topmost surface of the resistive switching layer, and the bottom electrode is locate entirely beneath the resistive switching layer.

### Claim 4 (depends on 1)

The semiconductor structure of claim 1, wherein the resistive random access memory stack includes a resistive switching layer and a top electrode, wherein the resistive switching layer is in direct physical contact with the faceted drain-side structure.

### Claim 5 (depends on 4)

The semiconductor structure of claim 4, wherein the top electrode has a topmost surface that is coplanar with a topmost surface of the resistive switching layer, and the bottom electrode is located entirely beneath the resistive switching layer.

### Claim 6 (depends on 1)

The semiconductor structure of claim 1, wherein the faceted drain-side structure has a triangular shape including a base and a tip, wherein the base is located on the topmost surface of the fully depleted semiconductor channel material layer, and the tip directly contacts the resistive random access memory stack.

### Claim 7 (depends on 1)

The semiconductor structure of claim 1, wherein the faceted drain-side structure comprises, from bottom to top, a drain-side doped semiconductor material and a drain-side metal semiconductor alloy.

### Claim 8 (depends on 1)

The semiconductor structure of claim 1, further comprising an interlayer dielectric (ILD) material laterally adjacent the resistive random access memory stack and the functional gate stack.

### Claim 9 (depends on 1)

The semiconductor structure of claim 1, further comprising a drain contact metal located on a surface of a top electrode of the resistive random access memory stack.

### Claim 10 (depends on 9)

The semiconductor structure of claim 9, further comprising a drain-side contact structure contacting the drain contact metal, a source-side contact structure contacting the faceted source-side structure, and a gate contact structure contacting a gate conductor of the functional gate structure.

### Claim 11 (depends on 1)

The semiconductor structure of claim 1, wherein the fully depleted semiconductor channel material layer is located on an insulator layer, and the insulator layer is located on a handle substrate.

### Claim 12 (depends on 1)

The semiconductor structure of claim 1, wherein an isolation structure surrounds the fully depleted semiconductor channel material layer.

### Claim 13

A method of forming a semiconductor structure, the method comprising:
forming a gate structure on a topmost surface of a fully depleted semiconductor channel material layer;
forming a faceted drain-side structure on the topmost surface of the fully depleted semiconductor channel material layer and on a first side of the gate structure, and a faceted source-side structure on the topmost surface of the fully depleted semiconductor channel material layer and on a second side of the gate structure that is opposite the first side;
forming an interlayer dielectric (ILD) material laterally adjacent the gate stack and atop the faceted drain-side structure, and atop the faceted source-side structure;
forming a contact opening in the ILD material to physically expose a surface of the faceted drain-side structure; and
forming a resistive random access memory stack in the contact opening and on the physically exposed surface of the faceted drain-side structure.

### Claim 14 (depends on 13)

The method of claim 13, wherein the forming the resistive random access memory stack comprises:
forming a bottom electrode layer in the drain-side contact opening and on the physically exposed surface of the faceted drain-side structure;
forming an organic planarization layer (OPL) on the bottom electrode;
removing vertical extending portions of the bottom electrode layer not protected by the OPL;
removing the OPL;
forming a resistive switching layer; and
forming a top electrode on the resistive switching layer.

### Claim 15 (depends on 13)

The method of claim 13, wherein the forming the resistive random access memory stack comprises:
forming a resistive switching layer in the drain-side contact opening and on the physically exposed surface of the faceted drain-side structure; and
forming a top electrode on the resistive switching layer.

### Claim 16 (depends on 13)

The method of claim 13, further comprising forming a drain contact metal on a surface of a top electrode of the resistive random access memory stack.

### Claim 17 (depends on 16)

The method of claim 16, further comprising forming a drain-side contact structure contacting the drain contact metal, a source-side contact structure contacting the faceted source-side structure, and a gate contact structure contacting a gate conductor of the gate structure.

### Claim 18 (depends on 13)

The method of claim 13, wherein the forming of the faceted drain-side structure comprises:
epitaxially growing a faceted and doped drain-side semiconductor material; and
forming a drain-side metal semiconductor alloy in an upper portion of the faceted and doped drain-side semiconductor material.

### Claim 19 (depends on 13)

The method of claim 13, wherein the fully depleted semiconductor channel material layer is located on an insulator layer, and the insulator layer is located on a handle substrate.

### Claim 20 (depends on 13)

The method of claim 13, wherein an isolation structure is formed surrounding the fully depleted semiconductor channel material layer.