# US 10,374,038 B2 · Semiconductor device source/drain region with arsenic-containing barrier region

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- Number: US 10,374,038 B2
- Document ID: US10374038B2
- Status: Granted
- Kind: B2
- Application number: 15/922,643
- Filed: 2018-03-15
- Published: 2019-05-30
- Granted: 2019-08-06
- Earliest claimed: 2017-11-24
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Chien-I Kuo; Chii-Horng Li; Chia-Ling Chan; Li-Li Su; Yi-Fang Pai; Wei Te Chiang; Shao-Fu Fu; Wei Hao Lu
- Web page: https://patentgrep.com/patent/US10374038B2

## CPC

- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 62/60: Impurity distributions or concentrations
- H10D 62/834: further characterised by the dopants
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P 14/24: using chemical vapour deposition [CVD]
- H10P 14/3402: {characterised by the chemical composition}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3442: {N-type}
- H10P 32/1204: {from a plasma phase}
- H10P 32/15: {from the substrate during epitaxy, e.g. autodoping; Preventing or using autodoping}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10P 50/242: {of Group IV materials}
- H10P 50/642: {Chemical etching}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

The present disclosure relates generally to an epitaxy scheme for forming source/drain regions in a semiconductor device, such as an n-channel device. In an example, a method of manufacturing a semiconductor device includes forming an active area on a substrate. The active area includes a source/drain region. The formation of the source/drain region includes forming a barrier region along a bottom surface and side surface of a recess in the active area. The barrier region includes arsenic having a first dopant concentration. The formation of the source/drain region further includes forming an epitaxial material on the barrier region in the recess. The epitaxial material includes phosphorous having a second dopant concentration.

## Claims

### Claim 1

A method of manufacturing a semiconductor device, the method comprising:
forming an active area on a substrate, the active area including a source/drain region, wherein forming the active area comprises:
forming a barrier region along a bottom surface and side surface of a recess in the active area, the barrier region comprising arsenic having a first dopant concentration; and
forming an epitaxial material on the barrier region in the recess, the epitaxial material comprising phosphorous having a second dopant concentration.

### Claim 2 (depends on 1)

The method of claim 1, wherein forming the barrier region comprises epitaxially growing the barrier region, the barrier region being in situ doped with the arsenic during the epitaxial growth.

### Claim 3 (depends on 1)

The method of claim 1, wherein forming the barrier region comprises plasma doping the active area through the bottom surface and side surface of the recess with the arsenic.

### Claim 4 (depends on 1)

The method of claim 1, wherein forming the barrier region comprises epitaxially growing the barrier region using a chemical vapor deposition (CVD) process, the barrier region being a SiAs layer.

### Claim 5 (depends on 1)

The method of claim 1, wherein the active area comprises a fin, and the semiconductor device is a n-channel Fin Field Effect Transistor (FinFET).

### Claim 6 (depends on 1)

The method of claim 1, wherein the first dopant concentration is in a range from about 1×1020 cm−3 to about 2×1021 cm−3.

### Claim 7 (depends on 1)

The method of claim 1, wherein a thickness of the barrier region is in a range from about 1 nanometer to about 20 nanometers.

### Claim 8 (depends on 1)

The method of claim 1 further comprising forming a gate structure over the active area, a sidewall of the gate structure most laterally proximate the source/drain region defining a plane, wherein a surface of the epitaxial material is less than 10 nm from the plane.

### Claim 9

A method of manufacturing a semiconductor device, the method comprising:
etching a recess in a fin proximate a gate structure, the gate structure being on the fin on a substrate;
forming a barrier region along a bottom surface and side surface of the recess, the barrier region comprising arsenic; and
epitaxially growing an epitaxial material on the barrier region, the epitaxial material comprising phosphorous.

### Claim 10 (depends on 9)

The method of claim 9, wherein forming the barrier region comprises:
epitaxially growing the barrier region in the recess.

### Claim 11 (depends on 10)

The method of claim 10, wherein epitaxially growing the barrier region comprises performing a chemical vapor deposition (CVD) process to grow a SiAs epitaxial layer as the barrier region.

### Claim 12 (depends on 9)

The method of claim 9, wherein forming the barrier region comprises doping the bottom surface and side surface of the recess with the arsenic.

### Claim 13 (depends on 9)

The method of claim 9, wherein forming the barrier region comprises plasma doping the bottom surface and side surface of the recess with the arsenic.

### Claim 14 (depends on 9)

The method of claim 9, wherein a dopant concentration of the arsenic in the barrier region is in a range from 1×1020 cm−3 to 2×1021 cm−3.

### Claim 15 (depends on 9)

The method of claim 9, wherein a thickness of the barrier region is in a range from 1 nanometer to 20 nanometers.

### Claim 16

A method of manufacturing a semiconductor device, the method comprising:
forming a first gate structure over a first semiconductor fin;
forming a first recess and a second recess in the first semiconductor fin on opposing sides of the first gate structure;
forming a barrier region along a bottom surface and side surface of the first recess and the second recess, the barrier region comprising arsenic; and
epitaxially growing an epitaxial material on the barrier region, the epitaxial material comprising an n-type dopant.

### Claim 17 (depends on 16)

The method of claim 16, wherein the n-type dopant comprises phosphorous.

### Claim 18 (depends on 16)

The method of claim 16, wherein forming the barrier region comprises a plasma doping process.

### Claim 19 (depends on 16)

The method of claim 16, wherein forming the barrier region comprises epitaxially growing the barrier region.

### Claim 20 (depends on 16)

The method of claim 16, wherein a dopant concentration of the arsenic in the barrier region is in a range from 1×1020 cm−3 to 2×1021 cm−3.