# US 10,374,035 B2 · Bulk nanosheet with dielectric isolation

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- Number: US 10,374,035 B2
- Document ID: US10374035B2
- Status: Granted
- Kind: B2
- Application number: 15/642,690
- Filed: 2017-07-06
- Published: 2017-10-26
- Granted: 2019-08-06
- Earliest claimed: 2015-10-21
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Kangguo Cheng; Bruce B. Doris; Junli Wang
- Web page: https://patentgrep.com/patent/US10374035B2

## CPC

- H10D 62/121: {oriented parallel to substrates}
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/118: {Nanostructure semiconductor bodies}
- H10D 62/364: {of IGFETs}
- H10D 62/834: further characterised by the dopants
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 86/01: Manufacture or treatment
- H10D 86/011: {comprising FinFETs}
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10D 86/215: {comprising FinFETs}
- H10P 90/1906: {Preparing SOI wafers}
- H10W 10/012: {using local oxidation of silicon [LOCOS]}
- H10W 10/0125: {comprising introducing electrical impurities in local oxidation regions, e.g. to alter LOCOS oxide growth characteristics}
- H10W 10/061: {using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations}
- H10W 10/13: formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]
- H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Techniques for dielectric isolation in bulk nanosheet devices are provided. In one aspect, a method of forming a nanosheet device structure with dielectric isolation includes the steps of: optionally implanting at least one dopant into a top portion of a bulk semiconductor wafer, wherein the at least one dopant is configured to increase an oxidation rate of the top portion of the bulk semiconductor wafer; forming a plurality of nanosheets as a stack on the bulk semiconductor wafer; patterning the nanosheets to form one or more nanowire stacks and one or more trenches between the nanowire stacks; forming spacers covering sidewalls of the nanowire stacks; and oxidizing the top portion of the bulk semiconductor wafer through the trenches, wherein the oxidizing step forms a dielectric isolation region in the top portion of the bulk semiconductor wafer. A nanowire FET and method for formation thereof are also provided.

## Claims

### Claim 1

A method of forming a nanowire field effect transistor (FET) device, the method comprising the steps of:
forming a plurality of nanosheets as a stack on a bulk semiconductor wafer, wherein the plurality of nanosheets comprises alternating layers of a sacrificial material and a channel material as the stack on the bulk semiconductor wafer;
patterning the nanosheets to form one or more nanowire stacks and one or more trenches between the nanowire stacks;
forming spacers covering sidewalls of the nanowire stacks;
oxidizing a top portion of the bulk semiconductor wafer through the trenches, wherein the oxidizing step forms a dielectric isolation region in the top portion of the bulk semiconductor wafer;
removing the spacers;
selectively removing portions of the layers of the sacrificial material from the nanowire stacks in a channel region of the FET device releasing portions of the channel material from the nanowire stacks, wherein the portions of the channel material released from the nanowire stacks form nanowire channels of the FET device, and wherein a first layer in the nanowire stacks comprises the sacrificial material and is present on the bulk semiconductor wafer; and
forming a gate surrounding the nanowire channels in the channel region of the FET device, wherein the first layer in the nanowire stacks has an inverted triangular shape beneath the gate in the channel region of the FET device.

### Claim 2 (depends on 1)

The method of claim 1, further comprising the step of:
forming a dopant implantation region in the top portion of the bulk semiconductor wafer, wherein the dopant implantation region comprises a dopant selected from the group consisting of: fluorine, phosphorous, and combinations thereof.

### Claim 3 (depends on 1)

The method of claim 1, further comprising the step of:
filling the trenches with a trench oxide prior to oxidizing the top portion of the bulk semiconductor wafer, wherein the trench oxide fully fills the trenches in between the spacers.

### Claim 4 (depends on 1)

The method of claim 1, further comprising the steps of:
forming at least one dummy gate over the nanowire stacks in the channel region of the FET device;
forming dummy gate spacers on opposite sides of the dummy gate;
forming doped source and drain regions of the FET device;
burying the dummy gate in a gap fill dielectric material;
removing the dummy gate forming at least one gate trench in the gap fill dielectric; and
forming the gate in the gate trench.

### Claim 5 (depends on 1)

The method of claim 1, wherein the gate is a metal gate that fully surrounds the nanowire channels in a gate-all-around (GAA) configuration.