# US 10,374,034 B1 · Undercut control in isotropic wet etch processes

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- Number: US 10,374,034 B1
- Document ID: US10374034B1
- Status: Granted
- Kind: B1
- Application number: 15/985,189
- Filed: 2018-05-21
- Granted: 2019-08-06
- Earliest claimed: 2018-05-21
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Chi-Chun Liu; Muthumanickam Sankarapandian; Kristin Schmidt; Ekmini Anuja De Silva; Noel Arellano; Robin Hsin Kuo Chao; Chun Wing Yeung; Zhenxing Bi
- Web page: https://patentgrep.com/patent/US10374034B1

## CPC

- H10D 62/118: {Nanostructure semiconductor bodies}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 62/119: {Nanowire, nanosheet or nanotube semiconductor bodies}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/122: {oriented at angles to substrates, e.g. perpendicular to substrates}
- H10D 62/364: {of IGFETs}
- H10D 64/01: Manufacture or treatment
- H10D 64/666: {the conductor further comprising additional layers}
- H10D 84/00: Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D 84/0177: {the gate conductors having different materials or different implants}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P 14/3464: {Nanotubes}
- H10P 14/69394: {the material containing titanium, e.g. TiO2}
- H10P 95/00: Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
- B82Y 40/00: Manufacture or treatment of nanostructures
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 84/0167: {Manufacturing their channels}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method for manufacturing a semiconductor device includes forming a first nanosheet device and forming a second nanosheet device spaced apart from the first nanosheet device in respective first and second regions corresponding to first and second types. The first and second nanosheet devices respectively include a first and a second plurality of work function metal layers, and a work function metal layer extends from the first and second plurality of work function metal layers in the space between the nanosheet devices. In the method, part of the work function metal layer is removed from the space between the nanosheet devices, and the removed part of the work function metal layer is replaced with a polymer brush layer. The first plurality of work function metal layers is selectively removed from the first region with respect to the polymer brush layer.

## Claims

### Claim 1

A method for manufacturing a semiconductor device, comprising:
forming a first nanosheet device in a first region corresponding to a first type, wherein the first nanosheet device comprises a first plurality of work function metal layers;
forming a second nanosheet device spaced apart from the first nanosheet device in a second region corresponding to a second type, wherein the second nanosheet device comprises a second plurality of work function metal layers, and wherein a work function metal layer extends from the first and second plurality of work function metal layers to a space between the first and second nanosheet devices;
forming an organic planarization layer in the second region covering the second nanosheet device and a first part of the work function metal layer in the space between the first and second nanosheet devices;
removing a second part of the work function metal layer not covered by the organic planarization layer from the space between the first and second nanosheet devices;
removing a portion of the first part of the work function metal layer under the organic planarization layer;
replacing removed areas of the work function metal layer with a polymer brush layer; and
selectively removing the first plurality of work function metal layers with respect to the polymer brush layer from the first region.

### Claim 2 (depends on 1)

The method according to claim 1, further comprising:
forming a first spacer layer on the first plurality of work function metal layers; and
forming a second spacer layer on the organic planarization layer.

### Claim 3 (depends on 2)

The method according to claim 2, wherein the first and second spacer layers comprise silicon oxide.

### Claim 4 (depends on 2)

The method according to claim 2, wherein a portion of the second part of the work function metal layer is removed from under the second spacer layer.

### Claim 5 (depends on 2)

The method according to claim 2, wherein a portion of the second part of the work function metal layer is removed from under the first spacer layer.

### Claim 6 (depends on 2)

The method according to claim 2, further comprising selectively removing the first and second spacer layers with respect to the polymer brush layer.

### Claim 7 (depends on 2)

The method according to claim 2, wherein a high-k dielectric layer is formed under the work function metal layer.

### Claim 8 (depends on 7)

The method according to claim 7, wherein replacing the removed areas of the work function metal layer with the polymer brush layer comprises selectively forming the polymer brush layer on the high-k dielectric layer.

### Claim 9 (depends on 7)

The method according to claim 7, wherein a material of the polymer brush layer grafts at a faster rate on the high-k dielectric layer than on the first and second spacer layers.

### Claim 10 (depends on 7)

The method according to claim 7, wherein a material of the polymer brush layer grafts at a faster rate on the high-k dielectric layer than on the organic planarization layer.

### Claim 11 (depends on 1)

The method according to claim 1, wherein replacing the removed areas of the work function metal layer with a polymer brush layer comprises performing an annealing process at a temperature in the range of about 120° C. to about 140° C.

### Claim 12 (depends on 1)

The method according to claim 1, further comprising:
removing part of the first plurality of work function metal layers from an upper portion of the first nanosheet device;
replacing the removed part of the first plurality of work function metal layers with another polymer brush layer.

### Claim 13 (depends on 1)

The method according to claim 1, further comprising removing the organic planarization layer and the polymer brush layer during the same removal process.

### Claim 14 (depends on 1)

The method according to claim 1, wherein the polymer brush layer comprises at least one of polystyrene, polytetrafluoroethylene, polyimide and polypropylene.

### Claim 15

A method for manufacturing a semiconductor device, comprising:
forming a first stacked transistor device in a first region corresponding to a first type, wherein the first stacked transistor device comprises a first plurality of work function metal layers;
forming a second stacked transistor device spaced apart from the first stacked transistor device in a second region corresponding to a second type, wherein the second stacked transistor device comprises a second plurality of work function metal layers, and wherein a work function metal layer extends from the first and second plurality of work function metal layers to a space between the first and second stacked transistor devices;
depositing a mask layer to cover the second stacked transistor device and portions adjacent the second stacked transistor device in the second region;
removing part of the work function metal layer from the space between the first and second stacked transistor devices;
replacing the removed part of the work function metal layer with a polymer brush layer; and
selectively removing the first plurality of work function metal layers with respect to the polymer brush layer from the first region.

### Claim 16

A method for manufacturing a semiconductor device, comprising:
forming a first plurality of stacked channel portions in a first region corresponding to a first type, wherein the first plurality of stacked channel portions are alternatingly stacked with a first plurality of work function metal layers;
forming a second plurality of stacked channel portions spaced apart from the first plurality of stacked channel portions in a second region corresponding to a second type, wherein the second plurality of stacked channel portions are alternatingly stacked with a second plurality of work function metal layers, and a work function metal layer extends from the first and second plurality of work function metal layers to a space between the first and second plurality of stacked channel portions;
forming an organic planarization layer in the second region covering the second plurality of stacked channel portions and covering a first part of the work function metal layer in the space between the first and second plurality of stacked channel portions;
removing a second part of the work function metal layer not covered by the organic planarization layer from the space between the first and second plurality of stacked channel portions;
removing a portion of the first part of the work function metal layer under the organic planarization layer;
replacing removed areas of the work function metal layer with a polymer brush layer; and
selectively removing the first plurality of work function metal layers with respect to the polymer brush layer from the first region.

### Claim 17 (depends on 16)

The method according to claim 16, further comprising:
forming a first spacer layer on the first plurality of work function metal layers; and
forming a second spacer layer on the organic planarization layer.

### Claim 18 (depends on 17)

The method according to claim 17, wherein a portion of the second part of the work function metal layer is removed from under the second spacer layer.

### Claim 19 (depends on 17)

The method according to claim 17, wherein a high-k dielectric layer is formed under the work function metal layer.

### Claim 20 (depends on 19)

The method according to claim 19, wherein replacing the removed areas of the work function metal layer with the polymer brush layer comprises selectively forming the polymer brush layer on the high-k dielectric layer.