# US 10,374,033 B1 · Semiconductor assemblies having semiconductor material regions with contoured upper surfaces

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- Number: US 10,374,033 B1
- Document ID: US10374033B1
- Status: Granted
- Kind: B1
- Application number: 15/915,158
- Filed: 2018-03-08
- Granted: 2019-08-06
- Earliest claimed: 2018-03-08
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Pranav P. Sharma; Vinay Nair; Sanjeev Sapra
- Web page: https://patentgrep.com/patent/US10374033B1

## CPC

- H10B 12/0335: {Making a connection between the transistor and the capacitor, e.g. plug}
- H10D 62/117: {Shapes of semiconductor bodies}
- H10B 12/30: {DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells}
- H10D 62/832: being Group IV materials comprising two or more elements, e.g. SiGe
- H10D 62/85: being Group III-V materials, e.g. GaAs
- H10W 44/601: {Capacitive arrangements (H10W44/20 takes precedence)}
- H10B 12/315: {with the capacitor higher than a bit line}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Some embodiments include an integrated assembly having a region of first semiconductor material. The region has an upper surface along a cross-section. The upper surface has a flat-topped peak and a concavity adjacent the flat-topped peak. A pillar of second semiconductor material is over the region and directly against the region. The pillar extends vertically from the upper surface. Some embodiments include a method of forming an integrated assembly. A construction is formed to have a semiconductor region, and to have an insulative region extending over the semiconductor region and alongside the semiconductor region. A combination of three etches is utilized to expose an upper surface of the semiconductor region and to modify the upper surface of the semiconductor region to form said upper surface to include, along a cross-section, a flat-topped peak portion and an adjacent concavity portion.

## Claims

### Claim 1

An integrated assembly, comprising:
a region of first semiconductor material; said region having a width along a cross-section; said region having an upper surface along the cross-section, with the upper surface having a flat-topped peak along one edge of the width, and having a concavity adjacent the flat-topped peak; and
a pillar of second semiconductor material over said region and directly against said region; the pillar extending vertically from said upper surface.

### Claim 2 (depends on 1)

The integrated assembly of claim 1 wherein the width is within a range of from 130 Å to 200 Å; and wherein a distance from the top of the flat-topped peak to the bottom of the concavity is within a range of from 20 Å to 50 Å.

### Claim 3 (depends on 1)

The integrated assembly of claim 1 wherein the first and second semiconductor materials are conductively doped; wherein a first digit line is laterally adjacent the second semiconductor material, and is laterally spaced from the second semiconductor material by a region of silicon nitride; and wherein a capacitor is over the second semiconductor material and is gatedly coupled with a second digit line through a conductive path which includes the first and second semiconductor materials.

### Claim 4 (depends on 3)

The integrated assembly of claim 3 wherein a portion of the second semiconductor material extends to under the region of the silicon nitride.

### Claim 5 (depends on 1)

The integrated assembly of claim 1 wherein the first semiconductor material comprises silicon.

### Claim 6 (depends on 1)

The integrated assembly of claim 1 wherein the first and second semiconductor materials comprise silicon and differ from one another in crystallinity.

### Claim 7 (depends on 1)

The integrated assembly of claim 1 wherein the first and second semiconductor materials comprise different elements relative to one another.

### Claim 8 (depends on 7)

The integrated assembly of claim 7 wherein the first semiconductor material comprises silicon, and wherein the second semiconductor material comprises one or more of germanium, III/V semiconductor material and semiconductor oxide.

### Claim 9 (depends on 1)

The integrated assembly of claim 1 wherein the first semiconductor material comprises monocrystalline silicon.

### Claim 10 (depends on 9)

The integrated assembly of claim 9 wherein the second semiconductor material comprises polycrystalline silicon.

### Claim 11

An integrated assembly, comprising:
first conductive material having an upper surface, wherein the upper surface comprises a first portion and a second portion that is concave downwardly from the first portion;
second conductive material over the first conductive material, wherein the second conductive material extends vertically from the first and second portions of the upper surface of the first conductive material; and
wherein the first conductive material serves as one of source and drain regions of an access transistor in a memory cell, and the second conductive material intervenes between the first conductive material and a lower electrode of a capacitor in the memory cell.